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Add support for riscv KVM and hugetlbfs. Using hugetlbfs instead of transparent huge pages can increase the performance.
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#[cfg(target_arch = "x86_64")] | ||
pub mod x86_64; | ||
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#[cfg(target_arch = "riscv64")] | ||
pub mod riscv; | ||
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#[cfg(target_arch = "x86_64")] | ||
pub use self::x86_64::vcpu; | ||
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#[cfg(target_arch = "riscv64")] | ||
pub use self::riscv::vcpu; |
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use kvm_bindings::*; | ||
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pub const SBI_CONSOLE_PUTCHAR: u64 = 0x01; | ||
pub const SBI_CONSOLE_GETCHAR: u64 = 0x02; | ||
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#[cfg(target_arch = "riscv32")] | ||
const KVM_REG_SIZE_ULONG: u64 = KVM_REG_SIZE_U32; | ||
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#[cfg(target_arch = "riscv64")] | ||
const KVM_REG_SIZE_ULONG: u64 = KVM_REG_SIZE_U64; | ||
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pub const KVM_REG_RISCV_CONFIG_ISA: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CONFIG as u64 | KVM_REG_SIZE_ULONG | 0x00; | ||
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pub const KVM_REG_RISCV_CORE_PC: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x00; | ||
pub const KVM_REG_RISCV_CORE_RA: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x01; | ||
pub const KVM_REG_RISCV_CORE_SP: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x02; | ||
pub const KVM_REG_RISCV_CORE_GP: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x03; | ||
pub const KVM_REG_RISCV_CORE_TP: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x04; | ||
pub const KVM_REG_RISCV_CORE_T0: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x05; | ||
pub const KVM_REG_RISCV_CORE_T1: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x06; | ||
pub const KVM_REG_RISCV_CORE_T2: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x07; | ||
pub const KVM_REG_RISCV_CORE_S0: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x08; | ||
pub const KVM_REG_RISCV_CORE_S1: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x09; | ||
pub const KVM_REG_RISCV_CORE_A0: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0a; | ||
pub const KVM_REG_RISCV_CORE_A1: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0b; | ||
pub const KVM_REG_RISCV_CORE_A2: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0c; | ||
pub const KVM_REG_RISCV_CORE_A3: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0d; | ||
pub const KVM_REG_RISCV_CORE_A4: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0e; | ||
pub const KVM_REG_RISCV_CORE_A5: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0f; | ||
pub const KVM_REG_RISCV_CORE_A6: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x10; | ||
pub const KVM_REG_RISCV_CORE_A7: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x11; | ||
pub const KVM_REG_RISCV_CORE_S2: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x12; | ||
pub const KVM_REG_RISCV_CORE_S3: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x13; | ||
pub const KVM_REG_RISCV_CORE_S4: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x14; | ||
pub const KVM_REG_RISCV_CORE_S5: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x15; | ||
pub const KVM_REG_RISCV_CORE_S6: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x16; | ||
pub const KVM_REG_RISCV_CORE_S7: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x17; | ||
pub const KVM_REG_RISCV_CORE_S8: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x18; | ||
pub const KVM_REG_RISCV_CORE_S9: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x19; | ||
pub const KVM_REG_RISCV_CORE_S10: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1a; | ||
pub const KVM_REG_RISCV_CORE_S11: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1b; | ||
pub const KVM_REG_RISCV_CORE_T3: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1c; | ||
pub const KVM_REG_RISCV_CORE_T4: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1d; | ||
pub const KVM_REG_RISCV_CORE_T5: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1e; | ||
pub const KVM_REG_RISCV_CORE_T6: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1f; | ||
pub const KVM_REG_RISCV_CORE_MODE: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x20; | ||
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pub const KVM_REG_RISCV_CSR_SSTATUS: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x00; | ||
pub const KVM_REG_RISCV_CSR_SIE: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x01; | ||
pub const KVM_REG_RISCV_CSR_STVEC: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x02; | ||
pub const KVM_REG_RISCV_CSR_SSCRATCH: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x03; | ||
pub const KVM_REG_RISCV_CSR_SEPC: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x04; | ||
pub const KVM_REG_RISCV_CSR_SCAUSE: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x05; | ||
pub const KVM_REG_RISCV_CSR_STVAL: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x06; | ||
pub const KVM_REG_RISCV_CSR_SIP: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x07; | ||
pub const KVM_REG_RISCV_CSR_SATP: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x08; | ||
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pub const KVM_REG_RISCV_TIMER_FREQUENCY: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x00; | ||
pub const KVM_REG_RISCV_TIMER_TIME: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x01; | ||
pub const KVM_REG_RISCV_TIMER_COMPARE: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x02; | ||
pub const KVM_REG_RISCV_TIMER_STATE: u64 = | ||
KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x03; | ||
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//TODO: RISC-V F-extension registers, RISC-V D-extension registers |
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pub mod consts; | ||
/// Arch riscv | ||
pub mod vcpu; |
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