Merge pull request #752 from stlankes/aarch64

remove some clippy warnings

src/arch/aarch64/kernel/interrupts.rs

@@ -260,11 +260,7 @@ pub fn init() {
 		let parts: Vec<_> = node.split('@').collect();
 
 		if let Some(compatible) = dtb.get_property(parts.first().unwrap(), "compatible") {
-			if core::str::from_utf8(compatible)
-				.unwrap()
-				.find("timer")
-				.is_some()
-			{
+			if core::str::from_utf8(compatible).unwrap().contains("timer") {
 				let irq_slice = dtb
 					.get_property(parts.first().unwrap(), "interrupts")
 					.unwrap();

src/arch/aarch64/kernel/pci.rs

@@ -63,14 +63,14 @@ impl ConfigRegionAccess for PciConfigRegion {
 
 /// Try to find regions for the device registers
 #[allow(unused_assignments)]
-fn detect_pci_regions(dtb: &Dtb<'_>, parts: &Vec<&str>) -> (u64, u64, u64) {
+fn detect_pci_regions(dtb: &Dtb<'_>, parts: &[&str]) -> (u64, u64, u64) {
 	let mut io_start: u64 = 0;
 	let mut mem32_start: u64 = 0;
 	let mut mem64_start: u64 = 0;
 
 	let mut residual_slice = dtb.get_property(parts.first().unwrap(), "ranges").unwrap();
 	let mut value_slice;
-	while residual_slice.len() > 0 {
+	while !residual_slice.is_empty() {
 		(value_slice, residual_slice) = residual_slice.split_at(core::mem::size_of::<u32>());
 		let high = u32::from_be_bytes(value_slice.try_into().unwrap());
 		(value_slice, residual_slice) = residual_slice.split_at(core::mem::size_of::<u32>());
@@ -128,7 +128,7 @@ fn detect_interrupt(
 	bus: u32,
 	dev: u32,
 	dtb: &Dtb<'_>,
-	parts: &Vec<&str>,
+	parts: &[&str],
 ) -> Option<(InterruptPin, InterruptLine)> {
 	let addr = bus << 16 | dev << 11;
 	if addr == 0 {
@@ -151,7 +151,7 @@ fn detect_interrupt(
 		.get_property(parts.first().unwrap(), "interrupt-map")
 		.unwrap();
 	let mut value_slice;
-	while residual_slice.len() > 0 {
+	while !residual_slice.is_empty() {
 		(value_slice, residual_slice) = residual_slice.split_at(core::mem::size_of::<u32>());
 		let high = u32::from_be_bytes(value_slice.try_into().unwrap());
 		(value_slice, residual_slice) = residual_slice.split_at(core::mem::size_of::<u32>());
@@ -208,7 +208,7 @@ fn detect_interrupt(
 			pin += 1;
 			if irq_type == 0 {
 				// enable interrupt
-				let irq_id = IntId::spi(irq_number.into());
+				let irq_id = IntId::spi(irq_number);
 				let gic = unsafe { GIC.get_mut().unwrap() };
 				gic.set_interrupt_priority(irq_id, 0x10);
 				if irq_flags == 4 {
@@ -240,8 +240,7 @@ pub fn init() {
 		if let Some(compatible) = dtb.get_property(parts.first().unwrap(), "compatible") {
 			if str::from_utf8(compatible)
 				.unwrap()
-				.find("pci-host-ecam-generic")
-				.is_some()
+				.contains("pci-host-ecam-generic")
 			{
 				let reg = dtb.get_property(parts.first().unwrap(), "reg").unwrap();
 				let (slice, residual_slice) = reg.split_at(core::mem::size_of::<u64>());
@@ -355,8 +354,7 @@ pub fn init() {
 				return;
 			} else if str::from_utf8(compatible)
 				.unwrap()
-				.find("pci-host-cam-generic")
-				.is_some()
+				.contains("pci-host-cam-generic")
 			{
 				warn!("Currently, pci-host-cam-generic isn't supported!");
 			}

src/arch/aarch64/kernel/serial.rs

@@ -6,9 +6,7 @@ pub struct SerialPort {
 
 impl SerialPort {
 	pub const fn new(port_address: u32) -> Self {
-		Self {
-			port_address: port_address,
-		}
+		Self { port_address }
 	}
 
 	pub fn write_byte(&self, byte: u8) {

src/arch/aarch64/kernel/systemtime.rs

@@ -58,7 +58,7 @@ pub fn init() {
 		let parts: Vec<_> = node.split('@').collect();
 
 		if let Some(compatible) = dtb.get_property(parts.first().unwrap(), "compatible") {
-			if str::from_utf8(compatible).unwrap().find("pl031").is_some() {
+			if str::from_utf8(compatible).unwrap().contains("pl031") {
 				let reg = dtb.get_property(parts.first().unwrap(), "reg").unwrap();
 				let (slice, residual_slice) = reg.split_at(core::mem::size_of::<u64>());
 				let addr = PhysAddr(u64::from_be_bytes(slice.try_into().unwrap()));

src/arch/aarch64/mm/paging.rs

@@ -41,19 +41,19 @@ bitflags! {
 		const TABLE_OR_4KIB_PAGE = 1 << 1;
 
 		/// Set if this entry points to device memory (non-gathering, non-reordering, no early write acknowledgement)
-		const DEVICE_NGNRNE = 0 << 4 | 0 << 3 | 0 << 2;
+		const DEVICE_NGNRNE = 0;
 
 		/// Set if this entry points to device memory (non-gathering, non-reordering, early write acknowledgement)
-		const DEVICE_NGNRE = 0 << 4 | 0 << 3 | 1 << 2;
+		const DEVICE_NGNRE = 1 << 2;
 
 		/// Set if this entry points to device memory (gathering, reordering, early write acknowledgement)
-		const DEVICE_GRE = 0 << 4 | 1 << 3 | 0 << 2;
+		const DEVICE_GRE = 1 << 3;
 
 		/// Set if this entry points to normal memory (non-cacheable)
-		const NORMAL_NC = 0 << 4 | 1 << 3 | 1 << 2;
+		const NORMAL_NC = 1 << 3 | 1 << 2;
 
 		/// Set if this entry points to normal memory (cacheable)
-		const NORMAL = 1 << 4 | 0 << 3 | 0 << 2;
+		const NORMAL = 1 << 4;
 
 		/// Set if memory referenced by this entry shall be read-only.
 		const READ_ONLY = 1 << 7;
@@ -271,14 +271,14 @@ impl<S: PageSize> Page<S> {
 		assert!(first.virtual_address <= last.virtual_address);
 		PageIter {
 			current: first,
-			last: last,
+			last,
 		}
 	}
 
 	/// Returns the index of this page in the table given by L.
 	fn table_index<L: PageTableLevel>(&self) -> usize {
 		assert!(L::LEVEL <= S::MAP_LEVEL);
-		self.virtual_address.as_usize() >> PAGE_BITS >> (3 - L::LEVEL) * PAGE_MAP_BITS
+		self.virtual_address.as_usize() >> PAGE_BITS >> ((3 - L::LEVEL) * PAGE_MAP_BITS)
 			& PAGE_MAP_MASK
 	}
 }