Merge pull request #27 from mossmann/cynthion_r1.3

Cynthion r1.3 support

firmware/Makefile

@@ -18,7 +18,7 @@ endif
 
 ifeq ($(BOARD), cynthion_d11)
 	# These should default to the latest revision but can be set on the command line.
-	BOARD_REVISION_MAJOR ?= 1
+	BOARD_REVISION_MAJOR ?= 3
 	BOARD_REVISION_MINOR ?= 0
 
 	# On r0.1 or r0.2 boards, we target the SAMD21 configuration.

firmware/src/boards/cynthion_d11/apollo_board.h

@@ -1,9 +1,7 @@
 /**
- * Apollo board definitions for SAMD11 Xplained hardware.
+ * Apollo board definitions for Cynthion r0.3 and above
  *
- * This file is part of LUNA.
- *
- * Copyright (c) 2020 Great Scott Gadgets <[email protected]>
+ * Copyright (c) 2020-2023 Great Scott Gadgets <[email protected]>
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
@@ -57,7 +55,11 @@ enum {
 #else
 	PROGRAM_BUTTON = PIN_PA02,
 	USB_SWITCH     = PIN_PA06,
-	FPGA_INT       = PIN_PA09,
+	FPGA_ADV       = PIN_PA09,
+#endif
+#if ((_BOARD_REVISION_MAJOR_ == 1) && (_BOARD_REVISION_MINOR_ > 2))
+	FPGA_INITN     = PIN_PA03,
+	FPGA_DONE      = PIN_PA04,
 #endif
 };
 

firmware/src/boards/cynthion_d11/fpga.c

@@ -11,6 +11,28 @@
 #include "apollo_board.h"
 #include "jtag.h"
 
+
+/*
+ * Allows or disallows the FPGA from configuring. When disallowed,
+ * initialization (erasing of configuration memory) takes place, but the FPGA
+ * does not proceed to the configuration phase.
+ */
+void permit_fpga_configuration(bool enable)
+{
+#if ((_BOARD_REVISION_MAJOR_ == 1) && (_BOARD_REVISION_MINOR_ > 2))
+	gpio_set_pin_level(FPGA_INITN, enable);
+	gpio_set_pin_direction(FPGA_INITN, GPIO_DIRECTION_OUT);
+
+	/*
+	 * Delay a bit (in case the FPGA is already initializing) because
+	 * TN-02039 says that PROGRAMN should not have a falling edge during
+	 * initialization.
+	 */
+	board_delay(1);
+#endif
+}
+
+
 /**
  * Sets up the I/O pins needed to configure the FPGA.
  */

firmware/src/boards/cynthion_d21/fpga.c

@@ -20,6 +20,16 @@ enum {
 };
 
 
+/*
+ * Allows or disallows the FPGA from configuring. When disallowed,
+ * initialization (erasing of configuration memory) takes place, but the FPGA
+ * does not proceed to the configuration phase.
+ */
+void permit_fpga_configuration(bool enable)
+{
+}
+
+
 /**
  * Sets up the I/O pins needed to configure the FPGA.
  */

firmware/src/boards/daisho/fpga.c

@@ -21,6 +21,16 @@ enum {
 };
 
 
+/*
+ * Allows or disallows the FPGA from configuring. When disallowed,
+ * initialization (erasing of configuration memory) takes place, but the FPGA
+ * does not proceed to the configuration phase.
+ */
+void permit_fpga_configuration(bool enable)
+{
+}
+
+
 static void fpga_initialize_power(void)
 {
 	gpio_t rail_enables[] = {

firmware/src/boards/qtpy/fpga.c

@@ -24,6 +24,16 @@ enum {
 #endif
 
 
+/*
+ * Allows or disallows the FPGA from configuring. When disallowed,
+ * initialization (erasing of configuration memory) takes place, but the FPGA
+ * does not proceed to the configuration phase.
+ */
+void permit_fpga_configuration(bool enable)
+{
+}
+
+
 /**
  * Sets up the I/O pins needed to configure the FPGA.
  */

firmware/src/boards/samd11_xplained/fpga.c

@@ -20,6 +20,16 @@ enum {
 };
 
 
+/*
+ * Allows or disallows the FPGA from configuring. When disallowed,
+ * initialization (erasing of configuration memory) takes place, but the FPGA
+ * does not proceed to the configuration phase.
+ */
+void permit_fpga_configuration(bool enable)
+{
+}
+
+
 /**
  * Sets up the I/O pins needed to configure the FPGA.
  */

firmware/src/fpga.h

@@ -15,6 +15,13 @@
  */
 void fpga_io_init(void);
 
+/*
+ * Allows or disallows the FPGA from configuring. When disallowed,
+ * initialization (erasing of configuration memory) takes place, but the FPGA
+ * does not proceed to the configuration phase.
+ */
+void permit_fpga_configuration(bool enable);
+
 /**
  * Requests that the FPGA clear its configuration and try to reconfigure.
  */

firmware/src/main.c

@@ -61,16 +61,25 @@ int main(void)
 		 */
                 force_fpga_offline();
                 take_over_usb();
+
+		/*
+		 * Now that the FPGA is being held offline, release the
+		 * mechanism that prevented the FPGA from configuring itself at
+		 * startup.
+		 */
+		permit_fpga_configuration(true);
 	} else {
 		/*
 		 * Normal start-up: Reconfigure FPGA from flash and hand off
 		 * the USB port to the FPGA. This effectively makes the RESET
 		 * button reset both the microcontroller and the FPGA.
 		 */
+		permit_fpga_configuration(true);
 		trigger_fpga_reconfiguration();
 		hand_off_usb();
 	}
 
+
 	while (1) {
 		tud_task(); // tinyusb device task
 		console_task();