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Merge branch 'qca8k-mirror-and-lag-support'
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Ansuel Smith says:

====================
Add mirror and LAG support to qca8k

With the continue of adding 'Multiple feature to qca8k'

The switch supports mirror mode and LAG.
In mirror mode a port is set as mirror and other port are configured
to both igress or egress mode. With no port configured for mirror,
the mirror port is disabled and reverted to normal port.

The switch supports max 4 LAG with 4 different member max.
Current supported mode is Hash mode in both L2 or L2+3 mode.
There is a problematic implementation for the hash mode where
with multiple LAG configured, someone has to remove them to
change the hash mode as it's global.
When a member of the LAG is disconnected, the traffic is redirected
to the other port.

Some warning are present from checkpatch but can't really be fixed
as it would result in making the regs less readable.
(They really did their best with the LAG reg logic and complexity)
====================

Signed-off-by: David S. Miller <[email protected]>
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@davem330
davem330 committed Nov 23, 2021
2 parents 1e84dc6 + def9753 commit 33e2ec5
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272 changes: 272 additions & 0 deletions drivers/net/dsa/qca8k.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1336,6 +1336,9 @@ qca8k_setup(struct dsa_switch *ds)
ds->ageing_time_min = 7000;
ds->ageing_time_max = 458745000;

/* Set max number of LAGs supported */
ds->num_lag_ids = QCA8K_NUM_LAGS;

return 0;
}

Expand Down Expand Up @@ -2022,6 +2025,99 @@ qca8k_port_mdb_del(struct dsa_switch *ds, int port,
return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
}

static int
qca8k_port_mirror_add(struct dsa_switch *ds, int port,
struct dsa_mall_mirror_tc_entry *mirror,
bool ingress)
{
struct qca8k_priv *priv = ds->priv;
int monitor_port, ret;
u32 reg, val;

/* Check for existent entry */
if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
return -EEXIST;

ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
if (ret)
return ret;

/* QCA83xx can have only one port set to mirror mode.
* Check that the correct port is requested and return error otherwise.
* When no mirror port is set, the values is set to 0xF
*/
monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
return -EEXIST;

/* Set the monitor port */
val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
mirror->to_local_port);
ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
if (ret)
return ret;

if (ingress) {
reg = QCA8K_PORT_LOOKUP_CTRL(port);
val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
} else {
reg = QCA8K_REG_PORT_HOL_CTRL1(port);
val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
}

ret = regmap_update_bits(priv->regmap, reg, val, val);
if (ret)
return ret;

/* Track mirror port for tx and rx to decide when the
* mirror port has to be disabled.
*/
if (ingress)
priv->mirror_rx |= BIT(port);
else
priv->mirror_tx |= BIT(port);

return 0;
}

static void
qca8k_port_mirror_del(struct dsa_switch *ds, int port,
struct dsa_mall_mirror_tc_entry *mirror)
{
struct qca8k_priv *priv = ds->priv;
u32 reg, val;
int ret;

if (mirror->ingress) {
reg = QCA8K_PORT_LOOKUP_CTRL(port);
val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
} else {
reg = QCA8K_REG_PORT_HOL_CTRL1(port);
val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
}

ret = regmap_clear_bits(priv->regmap, reg, val);
if (ret)
goto err;

if (mirror->ingress)
priv->mirror_rx &= ~BIT(port);
else
priv->mirror_tx &= ~BIT(port);

/* No port set to send packet to mirror port. Disable mirror port */
if (!priv->mirror_rx && !priv->mirror_tx) {
val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
if (ret)
goto err;
}
err:
dev_err(priv->dev, "Failed to del mirror port from %d", port);
}

static int
qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
struct netlink_ext_ack *extack)
Expand Down Expand Up @@ -2110,6 +2206,178 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
return DSA_TAG_PROTO_QCA;
}

static bool
qca8k_lag_can_offload(struct dsa_switch *ds,
struct net_device *lag,
struct netdev_lag_upper_info *info)
{
struct dsa_port *dp;
int id, members = 0;

id = dsa_lag_id(ds->dst, lag);
if (id < 0 || id >= ds->num_lag_ids)
return false;

dsa_lag_foreach_port(dp, ds->dst, lag)
/* Includes the port joining the LAG */
members++;

if (members > QCA8K_NUM_PORTS_FOR_LAG)
return false;

if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
return false;

if (info->hash_type != NETDEV_LAG_HASH_L2 ||
info->hash_type != NETDEV_LAG_HASH_L23)
return false;

return true;
}

static int
qca8k_lag_setup_hash(struct dsa_switch *ds,
struct net_device *lag,
struct netdev_lag_upper_info *info)
{
struct qca8k_priv *priv = ds->priv;
bool unique_lag = true;
int i, id;
u32 hash;

id = dsa_lag_id(ds->dst, lag);

switch (info->hash_type) {
case NETDEV_LAG_HASH_L23:
hash |= QCA8K_TRUNK_HASH_SIP_EN;
hash |= QCA8K_TRUNK_HASH_DIP_EN;
fallthrough;
case NETDEV_LAG_HASH_L2:
hash |= QCA8K_TRUNK_HASH_SA_EN;
hash |= QCA8K_TRUNK_HASH_DA_EN;
break;
default: /* We should NEVER reach this */
return -EOPNOTSUPP;
}

/* Check if we are the unique configured LAG */
dsa_lags_foreach_id(i, ds->dst)
if (i != id && dsa_lag_dev(ds->dst, i)) {
unique_lag = false;
break;
}

/* Hash Mode is global. Make sure the same Hash Mode
* is set to all the 4 possible lag.
* If we are the unique LAG we can set whatever hash
* mode we want.
* To change hash mode it's needed to remove all LAG
* and change the mode with the latest.
*/
if (unique_lag) {
priv->lag_hash_mode = hash;
} else if (priv->lag_hash_mode != hash) {
netdev_err(lag, "Error: Mismateched Hash Mode across different lag is not supported\n");
return -EOPNOTSUPP;
}

return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,
QCA8K_TRUNK_HASH_MASK, hash);
}

static int
qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,
struct net_device *lag, bool delete)
{
struct qca8k_priv *priv = ds->priv;
int ret, id, i;
u32 val;

id = dsa_lag_id(ds->dst, lag);

/* Read current port member */
ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);
if (ret)
return ret;

/* Shift val to the correct trunk */
val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);
val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;
if (delete)
val &= ~BIT(port);
else
val |= BIT(port);

/* Update port member. With empty portmap disable trunk */
ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,
QCA8K_REG_GOL_TRUNK_MEMBER(id) |
QCA8K_REG_GOL_TRUNK_EN(id),
!val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |
val << QCA8K_REG_GOL_TRUNK_SHIFT(id));

/* Search empty member if adding or port on deleting */
for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {
ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);
if (ret)
return ret;

val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);
val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;

if (delete) {
/* If port flagged to be disabled assume this member is
* empty
*/
if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
continue;

val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;
if (val != port)
continue;
} else {
/* If port flagged to be enabled assume this member is
* already set
*/
if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
continue;
}

/* We have found the member to add/remove */
break;
}

/* Set port in the correct port mask or disable port if in delete mode */
return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),
QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |
QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),
!delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |
port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));
}

static int
qca8k_port_lag_join(struct dsa_switch *ds, int port,
struct net_device *lag,
struct netdev_lag_upper_info *info)
{
int ret;

if (!qca8k_lag_can_offload(ds, lag, info))
return -EOPNOTSUPP;

ret = qca8k_lag_setup_hash(ds, lag, info);
if (ret)
return ret;

return qca8k_lag_refresh_portmap(ds, port, lag, false);
}

static int
qca8k_port_lag_leave(struct dsa_switch *ds, int port,
struct net_device *lag)
{
return qca8k_lag_refresh_portmap(ds, port, lag, true);
}

static const struct dsa_switch_ops qca8k_switch_ops = {
.get_tag_protocol = qca8k_get_tag_protocol,
.setup = qca8k_setup,
Expand All @@ -2132,6 +2400,8 @@ static const struct dsa_switch_ops qca8k_switch_ops = {
.port_fdb_dump = qca8k_port_fdb_dump,
.port_mdb_add = qca8k_port_mdb_add,
.port_mdb_del = qca8k_port_mdb_del,
.port_mirror_add = qca8k_port_mirror_add,
.port_mirror_del = qca8k_port_mirror_del,
.port_vlan_filtering = qca8k_port_vlan_filtering,
.port_vlan_add = qca8k_port_vlan_add,
.port_vlan_del = qca8k_port_vlan_del,
Expand All @@ -2141,6 +2411,8 @@ static const struct dsa_switch_ops qca8k_switch_ops = {
.phylink_mac_link_down = qca8k_phylink_mac_link_down,
.phylink_mac_link_up = qca8k_phylink_mac_link_up,
.get_phy_flags = qca8k_get_phy_flags,
.port_lag_join = qca8k_port_lag_join,
.port_lag_leave = qca8k_port_lag_leave,
};

static int qca8k_read_switch_id(struct qca8k_priv *priv)
Expand Down
37 changes: 37 additions & 0 deletions drivers/net/dsa/qca8k.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,8 @@
#define QCA8K_NUM_PORTS 7
#define QCA8K_NUM_CPU_PORTS 2
#define QCA8K_MAX_MTU 9000
#define QCA8K_NUM_LAGS 4
#define QCA8K_NUM_PORTS_FOR_LAG 4

#define PHY_ID_QCA8327 0x004dd034
#define QCA8K_ID_QCA8327 0x12
Expand Down Expand Up @@ -122,6 +124,14 @@
#define QCA8K_REG_EEE_CTRL 0x100
#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)

/* TRUNK_HASH_EN registers */
#define QCA8K_TRUNK_HASH_EN_CTRL 0x270
#define QCA8K_TRUNK_HASH_SIP_EN BIT(3)
#define QCA8K_TRUNK_HASH_DIP_EN BIT(2)
#define QCA8K_TRUNK_HASH_SA_EN BIT(1)
#define QCA8K_TRUNK_HASH_DA_EN BIT(0)
#define QCA8K_TRUNK_HASH_MASK GENMASK(3, 0)

/* ACL registers */
#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
Expand Down Expand Up @@ -180,6 +190,7 @@
#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
#define QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM GENMASK(7, 4)
#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
Expand All @@ -201,6 +212,29 @@
#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
#define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)

#define QCA8K_REG_GOL_TRUNK_CTRL0 0x700
/* 4 max trunk first
* first 6 bit for member bitmap
* 7th bit is to enable trunk port
*/
#define QCA8K_REG_GOL_TRUNK_SHIFT(_i) ((_i) * 8)
#define QCA8K_REG_GOL_TRUNK_EN_MASK BIT(7)
#define QCA8K_REG_GOL_TRUNK_EN(_i) (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
#define QCA8K_REG_GOL_TRUNK_MEMBER_MASK GENMASK(6, 0)
#define QCA8K_REG_GOL_TRUNK_MEMBER(_i) (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
/* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
#define QCA8K_REG_GOL_TRUNK_CTRL(_i) (0x704 + (((_i) / 2) * 4))
#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK GENMASK(3, 0)
#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK BIT(3)
#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK GENMASK(2, 0)
#define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i) (((_i) / 2) * 16)
#define QCA8K_REG_GOL_MEM_ID_SHIFT(_i) ((_i) * 4)
/* Complex shift: FIRST shift for port THEN shift for trunk */
#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j) (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))

#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
Expand Down Expand Up @@ -305,6 +339,9 @@ struct qca8k_ports_config {
struct qca8k_priv {
u8 switch_id;
u8 switch_revision;
u8 mirror_rx;
u8 mirror_tx;
u8 lag_hash_mode;
bool legacy_phy_port_mapping;
struct qca8k_ports_config ports_config;
struct regmap *regmap;
Expand Down

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