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wattson: Fix estimates when entire CPU track missing
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When an entire CPU freq or idle track is missing, then some other CPU
estimates won't be calculated.

Add a NULL but defined time range for CPUs that are physically present
on the device but don't have a single freq/idle event triggered. This is
so that interval_intersect() operates on a valid time range.

Test: tools/diff_test_trace_processor.py out/linux/trace_processor_shell --name-filter '.*wattson.*'
Bug: 379160886
Change-Id: I3b3fa24a61c2e348802b064e17d7dc93000f32b2
Signed-off-by: Samuel Wu <[email protected]>
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Samuel Wu committed Nov 14, 2024
1 parent 4ebd1d7 commit 1290ac2
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Showing 2 changed files with 25 additions and 2 deletions.
14 changes: 13 additions & 1 deletion src/trace_processor/perfetto_sql/stdlib/wattson/cpu_freq.sql
Original file line number Diff line number Diff line change
Expand Up @@ -51,4 +51,16 @@ SELECT
freq,
cpu,
policy
FROM _cpu_freq;
FROM _cpu_freq
UNION ALL
-- Add empty cpu freq counters for CPUs that are physically present, but did not
-- have a single freq event register. The time region needs to be defined so
-- that interval_intersect doesn't remove the undefined time region.
SELECT
trace_start() as ts,
trace_dur() as dur,
NULL as freq,
cpu,
NULL as policy
FROM _dev_cpu_policy_map
WHERE cpu NOT IN (SELECT cpu FROM first_cpu_freq_slices);
13 changes: 12 additions & 1 deletion src/trace_processor/perfetto_sql/stdlib/wattson/cpu_idle.sql
Original file line number Diff line number Diff line change
Expand Up @@ -91,4 +91,15 @@ SELECT
idle
FROM _cpu_idle
-- Some durations are 0 post-adjustment and won't work with interval intersect
WHERE dur > 0;
WHERE dur > 0
UNION ALL
-- Add empty cpu idle counters for CPUs that are physically present, but did not
-- have a single idle event register. The time region needs to be defined so
-- that interval_intersect doesn't remove the undefined time region.
SELECT
trace_start() as ts,
trace_dur() as dur,
cpu,
NULL as idle
FROM _dev_cpu_policy_map
WHERE cpu NOT IN (SELECT cpu FROM first_cpu_idle_slices);

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