math/big: Unify divWW implementation for ppc64 and ppc64le.

Starting in go1.9, the minimum processor requirement for ppc64 is POWER8. So it may now use the same divWW implementation as ppc64le. Updates #19074 Change-Id: If1a85f175cda89eee06a1024ccd468da6124c844 Reviewed-on: https://go-review.googlesource.com/39010 Run-TryBot: Brad Fitzpatrick <[email protected]> TryBot-Result: Gobot Gobot <[email protected]> Reviewed-by: Brad Fitzpatrick <[email protected]> Reviewed-by: Lynn Boger <[email protected]>
golang · Mar 31, 2017 · 4a11404 · 4a11404
1 parent 5a45a15
commit 4a11404
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diff --git a/src/math/big/arith_ppc64.s b/src/math/big/arith_ppc64.s
diff --git a/src/math/big/arith_ppc64le.s b/src/math/big/arith_ppc64le.s
diff --git a/src/math/big/arith_ppc64x.s b/src/math/big/arith_ppc64x.s
@@ -173,5 +173,44 @@ end:
 	MOVD R4, c+56(FP)
 	RET
 
+// func divWW(x1, x0, y Word) (q, r Word)
+TEXT ·divWW(SB), NOSPLIT, $0
+	MOVD x1+0(FP), R4
+	MOVD x0+8(FP), R5
+	MOVD y+16(FP), R6
+
+	CMPU R4, R6
+	BGE  divbigger
+
+	// from the programmer's note in ch. 3 of the ISA manual, p.74
+	DIVDEU R6, R4, R3
+	DIVDU  R6, R5, R7
+	MULLD  R6, R3, R8
+	MULLD  R6, R7, R20
+	SUB    R20, R5, R10
+	ADD    R7, R3, R3
+	SUB    R8, R10, R4
+	CMPU   R4, R10
+	BLT    adjust
+	CMPU   R4, R6
+	BLT    end
+
+adjust:
+	MOVD $1, R21
+	ADD  R21, R3, R3
+	SUB  R6, R4, R4
+
+end:
+	MOVD R3, q+24(FP)
+	MOVD R4, r+32(FP)
+
+	RET
+
+divbigger:
+	MOVD $-1, R7
+	MOVD R7, q+24(FP)
+	MOVD R7, r+32(FP)
+	RET
+
 TEXT ·divWVW(SB), NOSPLIT, $0
 	BR ·divWVW_g(SB)