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Support constraining AstSel (verilator#5344)
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Signed-off-by: Arkadiusz Kozdra <[email protected]>
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kozdra authored Aug 8, 2024
1 parent 78555b6 commit 3e5859e
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Showing 3 changed files with 20 additions and 0 deletions.
1 change: 1 addition & 0 deletions src/V3AstNodeExpr.h
Original file line number Diff line number Diff line change
Expand Up @@ -4678,6 +4678,7 @@ class AstSel final : public AstNodeTriop {
: isWide() ? "VL_SEL_%nq%lq%rq%tq(%nw,%lw, %P, %li, %ri, %ti)"
: "VL_SEL_%nq%lq%rq%tq(%lw, %P, %li, %ri, %ti)";
}
string emitSMT() const override { return "((_ extract %t %r) %l)"; }
bool cleanOut() const override { return false; }
bool cleanLhs() const override { return true; }
bool cleanRhs() const override { return true; }
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16 changes: 16 additions & 0 deletions src/V3Randomize.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -529,6 +529,22 @@ class ConstraintExprVisitor final : public VNVisitor {
if (editFormat(nodep)) return;
editSMT(nodep, nodep->srcp());
}
void visit(AstSel* nodep) override {
if (editFormat(nodep)) return;
VNRelinker handle;
AstNodeExpr* const widthp = nodep->widthp()->unlinkFrBack(&handle);
FileLine* const fl = nodep->fileline();
AstNodeExpr* const msbp
= new AstSFormatF{fl, "%1d", false,
new AstAdd{fl, nodep->lsbp()->cloneTreePure(false),
new AstSub{fl, widthp, new AstConst{fl, 1}}}};
handle.relink(msbp);
AstNodeExpr* const lsbp
= new AstSFormatF{fl, "%1d", false, nodep->lsbp()->unlinkFrBack(&handle)};
handle.relink(lsbp);

editSMT(nodep, nodep->fromp(), lsbp, msbp);
}
void visit(AstSFormatF* nodep) override {}
void visit(AstStmtExpr* nodep) override {}
void visit(AstConstraintIf* nodep) override {
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3 changes: 3 additions & 0 deletions test_regress/t/t_constraint_operators.v
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ class Packet;
rand int x;
rand bit [31:0] b;
rand bit [31:0] c;
rand bit [31:0] d;
rand bit tiny;
rand bit zero;
rand bit one;
Expand All @@ -31,6 +32,7 @@ class Packet;
constraint cond { (tiny == 1 ? b : c) != 17; }
constraint zero_c { zero == 0; }
constraint one_c { one == 1; }
constraint sel { d[15:8] == 8'h55; }
constraint ifelse {
if (one == 1) out0 == 'h333;

Expand Down Expand Up @@ -88,6 +90,7 @@ module t (/*AUTOARG*/);
if (p.out4 != 'h333) $stop;
if (p.out5 != 'h333) $stop;
if (p.out6 != 'h333) $stop;
if (p.d[15:8] != 'h55) $stop;

$write("*-* All Finished *-*\n");
$finish;
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