UART: fix spurios character on some FPGAs after config

build.sbt

@@ -17,7 +17,7 @@ lazy val publishSettings = Seq (
   // disable publish with scala version, otherwise artifact name will include scala version 
   // e.g cassper_2.11
   // MS: maybe we should enable this again
-  crossPaths := true,
+  crossPaths := false,
 
   // add sonatype repository settings
   // snapshot versions publish to sonatype snapshot repository

src/main/scala/chisel/lib/uart/Uart.scala

@@ -15,10 +15,10 @@ import chisel3.util._
 class UartIO extends DecoupledIO(UInt(8.W))
 
 /**
-  * Transmit part of the UART.
-  * A minimal version without any additional buffering.
-  * Use a ready/valid handshaking.
-  */
+ * Transmit part of the UART.
+ * A minimal version without any additional buffering.
+ * Use a ready/valid handshaking.
+ */
 class Tx(frequency: Int, baudRate: Int) extends Module {
   val io = IO(new Bundle {
     val txd = Output(UInt(1.W))
@@ -56,42 +56,43 @@ class Tx(frequency: Int, baudRate: Int) extends Module {
 }
 
 /**
-  * Receive part of the UART.
-  * A minimal version without any additional buffering.
-  * Use a ready/valid handshaking.
-  *
-  * The following code is inspired by Tommy's receive code at:
-  * https://github.com/tommythorn/yarvi
-  */
+ * Receive part of the UART.
+ * A minimal version without any additional buffering.
+ * Use a ready/valid handshaking.
+ *
+ * The following code is inspired by Tommy's receive code at:
+ * https://github.com/tommythorn/yarvi
+ */
 class Rx(frequency: Int, baudRate: Int) extends Module {
   val io = IO(new Bundle {
     val rxd = Input(UInt(1.W))
     val channel = new UartIO()
   })
 
-  val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U
-  val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 1).U
+  val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1)
+  val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 2) // -2 for the falling delay
 
-  // Sync in the asynchronous RX data, reset to 1 to not start reading after a reset
-  val rxReg = RegNext(RegNext(io.rxd, 1.U), 1.U)
+  // Sync in the asynchronous RX data
+  val rxReg = RegNext(RegNext(io.rxd, 0.U), 0.U)
+  val falling = !rxReg && (RegNext(rxReg) === 1.U)
 
   val shiftReg = RegInit(0.U(8.W))
-  val cntReg = RegInit(0.U(20.W))
+  val cntReg = RegInit(BIT_CNT.U(20.W)) // have some idle time before listening
   val bitsReg = RegInit(0.U(4.W))
   val valReg = RegInit(false.B)
 
   when(cntReg =/= 0.U) {
     cntReg := cntReg - 1.U
   }.elsewhen(bitsReg =/= 0.U) {
-    cntReg := BIT_CNT
+    cntReg := BIT_CNT.U
     shiftReg := Cat(rxReg, shiftReg >> 1)
     bitsReg := bitsReg - 1.U
     // the last shifted in
     when(bitsReg === 1.U) {
       valReg := true.B
     }
-  }.elsewhen(rxReg === 0.U) { // wait 1.5 bits after falling edge of start
-    cntReg := START_CNT
+  }.elsewhen(falling) { // wait 1.5 bits after falling edge of start
+    cntReg := START_CNT.U
     bitsReg := 8.U
   }
 
@@ -104,8 +105,8 @@ class Rx(frequency: Int, baudRate: Int) extends Module {
 }
 
 /**
-  * A single byte buffer with a ready/valid interface
-  */
+ * A single byte buffer with a ready/valid interface
+ */
 class Buffer extends Module {
   val io = IO(new Bundle {
     val in = Flipped(new UartIO())
@@ -133,8 +134,8 @@ class Buffer extends Module {
 }
 
 /**
-  * A transmitter with a single buffer.
-  */
+ * A transmitter with a single buffer.
+ */
 class BufferedTx(frequency: Int, baudRate: Int) extends Module {
   val io = IO(new Bundle {
     val txd = Output(UInt(1.W))
@@ -149,8 +150,8 @@ class BufferedTx(frequency: Int, baudRate: Int) extends Module {
 }
 
 /**
-  * Send a string.
-  */
+ * Send a string.
+ */
 class Sender(frequency: Int, baudRate: Int) extends Module {
   val io = IO(new Bundle {
     val txd = Output(UInt(1.W))
@@ -203,7 +204,6 @@ class UartMain(frequency: Int, baudRate: Int) extends Module {
     e.io.rxd := io.rxd
     io.txd := e.io.txd
   }
-
 }
 
 object UartMain extends App {