First patches for HS5x support.

foss-for-synopsys-dwc-arc-processors · Dec 10, 2021 · bfb057c · bfb057c
1 parent fcf2a36
commit bfb057c
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Showing 9 changed files with 121 additions and 141 deletions.
diff --git a/include/elf.h b/include/elf.h
@@ -211,6 +211,7 @@ typedef struct mips_elf_abiflags_v0 {
 #define EM_ARC_COMPACT  93  /* Synopsys ARCompact */
 #define EM_ARC_COMPACT2 195 /* Synopsys ARCompact V2 */
 #define EM_ARC_COMPACT3_64 253 /* Synopsys ARCompact V3 ARC64 */
+#define EM_ARC_COMPACT3_32 255 /* Synopsys ARCompact V3 ARC64 */
 
 #define EM_MOXIE           223     /* Moxie processor family */
 #define EM_MOXIE_OLD       0xFEED

diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
@@ -344,6 +344,14 @@ static int glue(load_elf, SZ)(const char *name, int fd,
     }
 
     switch (elf_machine) {
+        case EM_ARC_COMPACT3_64:
+            if (ehdr.e_machine != EM_ARC_COMPACT3_64) {
+                if (ehdr.e_machine != EM_ARC_COMPACT3_32) {
+                    ret = ELF_LOAD_WRONG_ARCH;
+                    goto fail;
+                }
+            }
+            break;
         case EM_PPC64:
             if (ehdr.e_machine != EM_PPC64) {
                 if (ehdr.e_machine != EM_PPC) {

diff --git a/target/arc/cpu.c b/target/arc/cpu.c
@@ -210,6 +210,9 @@ static void arc_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
     case ARC_OPCODE_V3_ARC64:
         info->mach = bfd_mach_arcv3_64;
         break;
+    case ARC_OPCODE_V3_ARC32:
+        info->mach = bfd_mach_arcv3_32;
+        break;
     default:
         info->mach = bfd_mach_arc_arcv2;
         break;
@@ -370,7 +373,18 @@ static ObjectClass *arc_cpu_class_by_name(const char *cpu_model)
 
 static gchar *arc_gdb_arch_name(CPUState *cs)
 {
+#if defined(TARGET_ARCV2)
     return g_strdup(GDB_TARGET_STRING);
+#elif defined(TARGET_ARCV3)
+    ARCCPU *cpu = ARC_CPU(cs);
+    if(cpu->family & ARC_OPCODE_V3_ARC64) {
+        return g_strdup(GDB_TARGET_STRING);
+    } else {
+        return g_strdup("arc64:32");
+    }
+#else
+#error "Not possible to happen"
+#endif
 }
 
 #include "hw/core/tcg-cpu-ops.h"
@@ -464,6 +478,12 @@ static void arc_hs6x_initfn(Object *obj)
     ARCCPU *cpu = ARC_CPU(obj);
     cpu->family = ARC_OPCODE_V3_ARC64;
 }
+
+static void arc_hs5x_initfn(Object *obj)
+{
+    ARCCPU *cpu = ARC_CPU(obj);
+    cpu->family = ARC_OPCODE_V3_ARC32;
+}
 #endif
 
 typedef struct ARCCPUInfo {
@@ -480,6 +500,7 @@ static const ARCCPUInfo arc_cpus[] = {
 #endif
 #ifdef TARGET_ARCV3
     { .name = "hs6x", .initfn = arc_hs6x_initfn },
+    { .name = "hs5x", .initfn = arc_hs5x_initfn },
 #endif
     { .name = "any", .initfn = arc_any_initfn },
 };

diff --git a/target/arc/decoder-v3.c b/target/arc/decoder-v3.c
@@ -1331,6 +1331,7 @@ unsigned int arc_insn_length(uint16_t insn, uint16_t cpu_type)
 
     switch (cpu_type) {
       case ARC_OPCODE_V3_ARC64:
+      case ARC_OPCODE_V3_ARC32:
           if(major_opcode == 0x0b)
             return 4;
           return (major_opcode > 0x7) ? 2 : 4;

diff --git a/target/arc/helper.c b/target/arc/helper.c
@@ -84,7 +84,7 @@ void arc_cpu_do_interrupt(CPUState *cs)
         env->mpu.enabled = false;     /* no more MPU */
     }
     vectno = cs->exception_index & 0x0F;
-    offset = OFFSET_FOR_VECTOR(vectno);
+    offset = OFFSET_FOR_VECTOR(cpu, vectno);
 
     /* Generic computation for exceptions. */
     switch (cs->exception_index) {
@@ -218,7 +218,14 @@ void arc_cpu_do_interrupt(CPUState *cs)
                                 MEMTXATTRS_UNSPECIFIED, &txres);
     assert(txres == MEMTX_OK);
 #elif defined(TARGET_ARCV3)
-    env->pc = cpu_ldq_data(env, env->intvec + offset);
+    switch(cpu->family) {
+      case ARC_OPCODE_V3_ARC64:
+        env->pc = cpu_ldq_data(env, env->intvec + offset);
+        break;
+      case ARC_OPCODE_V3_ARC32:
+        env->pc = cpu_ldl_data(env, env->intvec + offset);
+        break;
+    }
 #else
 #error "This should never happen !!!!"
 #endif

diff --git a/target/arc/irq.c b/target/arc/irq.c
@@ -34,8 +34,25 @@
 #define TARGET_LONG_LOAD(ENV, ADDR) cpu_ldl_data(ENV, ADDR)
 #define TARGET_LONG_STORE(ENV, ADDR, VALUE) cpu_stl_data(ENV, ADDR, VALUE)
 #elif defined(TARGET_ARCV3)
-#define TARGET_LONG_LOAD(ENV, ADDR) cpu_ldq_data(ENV, ADDR)
-#define TARGET_LONG_STORE(ENV, ADDR, VALUE) cpu_stq_data(ENV, ADDR, VALUE)
+static inline target_ulong
+TARGET_LONG_LOAD(CPUARCState *env, target_ulong addr) {
+    ARCCPU *cpu = env_archcpu(env);
+    if((cpu->family & ARC_OPCODE_V3_ARC64) != 0) {
+	return cpu_ldq_data(env, addr);
+    } else {
+	return cpu_ldl_data(env, addr);
+    }
+}
+static inline void
+TARGET_LONG_STORE(CPUARCState *env, target_ulong addr,
+		  target_ulong value) {
+    ARCCPU *cpu = env_archcpu(env);
+    if((cpu->family & ARC_OPCODE_V3_ARC64) != 0) {
+	cpu_stq_data(env, addr, value);
+    } else {
+	cpu_stq_data(env, addr, value);
+    }
+}
 #else
 #error "This should never happen !!!!"
 #endif
@@ -569,7 +586,7 @@ bool arc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     }
 
     /* XX. The PC is set with the appropriate exception vector. */
-    offset = OFFSET_FOR_VECTOR(vectno);
+    offset = OFFSET_FOR_VECTOR(cpu, vectno);
     env->pc = TARGET_LONG_LOAD(env, env->intvec + offset);
     CPU_PCL(env) = env->pc & (~((target_ulong) 3));
 

diff --git a/target/arc/irq.h b/target/arc/irq.h
@@ -31,9 +31,13 @@ void arc_initializeIRQ(ARCCPU *);
 void arc_resetIRQ(ARCCPU *);
 
 #if defined(TARGET_ARCV2)
-#define OFFSET_FOR_VECTOR(VECNO) (VECNO << 2)
+#define OFFSET_FOR_VECTOR(CPU, VECNO) (VECNO << 2)
 #elif defined(TARGET_ARCV3)
-#define OFFSET_FOR_VECTOR(VECNO) (VECNO << 3)
+#define OFFSET_FOR_VECTOR(CPU, VECNO) \
+  ((cpu->family & ARC_OPCODE_V3_ARC64) != 0) ? \
+  (VECNO << 3) : \
+  (VECNO << 2)
+
 #else
 #error Should never be reached
 #endif

diff --git a/target/arc/semfunc-helper.h b/target/arc/semfunc-helper.h
@@ -370,6 +370,29 @@ void tcg_gen_shlfi_tl(TCGv a, int b, TCGv c);
 //#define se32to64(A, B) gen_helper_se32to64(A, B)
 #define se32to64(A, B) tcg_gen_ext32s_tl(A, B)
 
+#define ARC64_ADDRESS_ADD(A, B, C) { \
+  ARCCPU *cpu = env_archcpu(ctx->env); \
+  if((cpu->family & ARC_OPCODE_V3_ARC64) != 0) { \
+    tcg_gen_add_tl(A, B, C); \
+  } else if((cpu->family & ARC_OPCODE_V3_ARC32) != 0) { \
+    TCGv_i32 tA, tB, tC; \
+    tA = tcg_temp_new_i32(); \
+    tB = tcg_temp_new_i32(); \
+    tC = tcg_temp_new_i32(); \
+    \
+    tcg_gen_extrl_i64_i32(tB, B); \
+    tcg_gen_extrl_i64_i32(tC, C); \
+    tcg_gen_add_i32(tA, tB, tC); \
+    tcg_gen_extu_i32_i64(A, tA); \
+    \
+    tcg_temp_free_i32(tA); \
+    tcg_temp_free_i32(tB); \
+    tcg_temp_free_i32(tC); \
+  } else { \
+    assert(0); \
+  } \
+}
+
 #endif
 
 #endif /* SEMFUNC_HELPER_H_ */