ARC: SMP resurrect #18: clocksource related fixes for non-boot CPU

We can only have one system wide clocksource, which is backed by
boot-cpu's hardware free flowing counter (TIMER1). Thus the clocksource
registration for non boot CPU was simply wrong.

However since the clocksource counter can't be accessed from "other"
cpus, which need it for timer interpolation for a local gtod call, we
nevertheless setup the "other" cpu counter - albeit w/o clocksource.
Due to different starting points, these counters are certainly not
synchronized, which we live with - fixing purely in software would
require conveying the lag from boot-cpu to them and then makign the
corresponding adjustments [see arch/x86/kernel/tsc.c].

However, any recent release of ARC700 (which will run SMP) will have
a 64-bit raw cycle counter (accessed with RTSC insn) which _shd_ be
precisely synchronized across CPUs

Signed-off-by: Vineet Gupta <[email protected]>

arch/arc/include/asm/irq.h

@@ -16,7 +16,7 @@ extern void __init arc_init_IRQ(void);
 extern void __init plat_init_IRQ(void);
 extern int get_hw_config_num_irq(void);
 
-void __cpuinit arc_clocksource_init(void);
 void __cpuinit arc_clockevent_init(void);
+void __cpuinit arc_clock_counter_setup(void);
 
 #endif

arch/arc/kernel/smp.c

@@ -113,7 +113,15 @@ void __cpuinit start_kernel_secondary(void)
 
 	arc_platform_smp_init_cpu();
 
-	arc_clocksource_init();
+	/*
+	 * XXX: Note that TIMER1 based cpu-local counters will not be
+	 * synchronized given the time lag between time_init (boot-cpu only)
+	 * vs. the time we reach here. However assuming that any SMP Linux
+	 * deployments will use a recent enough ARC700 with a perfectly
+	 * synchronized 64-bit CPU cycle counter backing the RTSC insn.
+	 */
+	arc_clock_counter_setup();
+
 	arc_clockevent_init();
 
 	local_irq_enable();

arch/arc/kernel/time.c

@@ -82,8 +82,10 @@ static void arc_timer0_ack_event(unsigned int irq_reenable)
 /*
  * Arm the timer to keep counting monotonically
  */
-static void arc_timer1_setup_free_flow(unsigned int limit)
+void __cpuinit arc_clock_counter_setup(void)
 {
+	unsigned int limit = ARC_TIMER_MAX;
+
 	/* although for free flowing case, limit would alway be max 32 bits
 	 * still we've kept the interface open, just in case ...
 	 */
@@ -109,7 +111,7 @@ static struct clocksource clocksource_t1 = {
 
 void __cpuinit arc_clocksource_init(void)
 {
-	arc_timer1_setup_free_flow(ARC_TIMER_MAX);
+	arc_clock_counter_setup();
 
 	/*
 	 * CLK upto 4.29 GHz can be safely represented in 32 bits because