ARCv2: Add SLC-related AUX regs

 1. ARC_REG_SLC_CFG_BCR is not a BCR (Build configuration register) but
a simple AUX reg for SLC control. Any BCR AUX reg could be read always
and that's safe while attempt to even read AUX reg that corresponds to
missing HW block will inevitably lead to "Instruciton Error" exception.
So to prevent users from misuse of that AUX register we'll remove "_BCR"
suffix from its name
 2. To manage SLC we'll need more AUX regs for:
     * SLC enable/disable (ARC_REG_SLC_CONTROL)
     * full flush (ARC_REG_SLC_FLUSH)
     * full invaludation (ARC_REG_SLC_INVALIDATE)

Signed-off-by: Alexey Brodkin <[email protected]>

arch/arc/include/asm/arcregs.h

@@ -36,7 +36,6 @@
 #define ARC_REG_ISA_CFG_BCR	0xc1
 #define ARC_REG_RTT_BCR		0xF2
 #define ARC_REG_SMART_BCR	0xFF
-#define ARC_REG_SLC_CFG_BCR	0x901
 
 /* status32 Bits Positions */
 #define STATUS_AE_BIT		5	/* Exception active */

arch/arc/include/asm/cache.h

@@ -82,4 +82,13 @@ extern void read_decode_cache_bcr(void);
 #define DC_CTRL_INV_MODE_FLUSH  0x40
 #define DC_CTRL_FLUSH_STATUS    0x100
 
+/*System-level cache (SLC) related Auxiliary registers */
+#define ARC_REG_SLC_CFG		0x901
+#define ARC_REG_SLC_CONTROL	0x903
+#define ARC_REG_SLC_FLUSH	0x904
+#define ARC_REG_SLC_INVALIDATE	0x905
+
+/* Bit val in SLC_CONTROL */
+#define SLC_CONTROL_DISABLE	0x1
+
 #endif /* _ASM_CACHE_H */

arch/arc/mm/cache_arc700.c

@@ -172,7 +172,7 @@ void read_decode_cache_bcr(void)
 	p_slc = &cpuinfo_arc700[cpu].slc;
 	READ_BCR(ARC_REG_SLC_BCR, sbcr);
 	if (sbcr.ver) {
-		READ_BCR(ARC_REG_SLC_CFG_BCR, slc_cfg);
+		READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
 		p_slc->ver = sbcr.ver;
 		p_slc->sz_k = 128 << slc_cfg.sz;
 		p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64;