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rtm.py : fix wrong commit on #634 (isConnected() and False: ) #978

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Apr 16, 2016
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2 changes: 1 addition & 1 deletion python/rtm.py
Original file line number Diff line number Diff line change
Expand Up @@ -538,7 +538,7 @@ def connectPorts(outP, inPs, subscription="flush", dataflow="Push", bufferlength
print('[rtm.py] \033[31m Failed to connect %s to %s(%s)\033[0m' % \
(outP.get_port_profile().name, inP, inPs))
continue
if isConnected(outP, inP) == True and False:
if isConnected(outP, inP) == True:
print('[rtm.py] %s and %s are already connected' % \
(outP.get_port_profile().name, inP.get_port_profile().name))
continue
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24 changes: 24 additions & 0 deletions test/test-hrpsysconf.py
Original file line number Diff line number Diff line change
Expand Up @@ -23,12 +23,29 @@ def init(self, robotname="SampleRobot(Robot)0", url=""):

class TestHrpsysConfig(unittest.TestCase):
global h
rh = None
seq = None

def test_import_waitinput(self):
# https://github.com/start-jsk/rtmros_hironx/blob/groovy-devel/hironx_ros_bridge/src/hironx_ros_bridge/hironx_client.py
from waitInput import waitInputConfirm, waitInputSelect
self.assertTrue(True)

def test_createcomp(self):
global h
self.seq = h.createComp("SequencePlayer",'seq')[0]

def test_connectcomp(self):
global h
if self.seq == None or self.rh == None:
self.test_createcomp()
connectPorts(self.rh.port("q"), self.seq.port("qInit"))
# check number of connection
assert(len(self.seq.port("qInit").get_connector_profiles()) == 1)
# check do not connect again if already connected for https://github.com/fkanehiro/hrpsys-base/issues/979
connectPorts(self.rh.port("q"), self.seq.port("qInit"))
assert(len(self.seq.port("qInit").get_connector_profiles()) == 1)

def test_findcomp(self):
global h
h.findComps()
Expand All @@ -46,6 +63,13 @@ def setUp(self):
rtm.nsport = args.port
h = SampleHrpsysConfigurator()

h.waitForRTCManager()
# look for name
for c in h.ms.get_components():
if '(Robot)' in c.name() or 'RobotHardware' in c.name():
h.waitForRobotHardware(c.name()) # get robot hardware name
break;
self.rh = h.rh

#unittest.main()
if __name__ == '__main__':
Expand Down