2019_05_10

• Important items to follow up on:
  • Data collection - see Brian's note above
  • Data access - need to talk to Jason about data prep scripts, location, infrastructure
  • Board progress
    • Work in simulator?
      • Yes, doing this, but also...
    • Got a Cyclone 5 for toolchain testing (off project acquisition)
      • Does HLS support Cyclone 5 (bare minimum!)
      • Simple test on "Ed's" rig - he can add a LabView control scheme very easily?
      • Want a network running on hardware by sometime next month.
        • Plan is not to use a Cyclone 5, but just to test the workflow.
        • Where are we on this?
          • Played around with building MLP on Aria-10, Quartus-prime (we have pro version, so we can do big FPGAs)
          • Made the verilog
          • Did some resource estimation with Quartus, need to figure out how to do resource optimization
            • But, point is that it runs out of the box and can be iterated on
            • All simulation at this point (don't have access to an Aria-10)
          • Want to get all the numbers based on simulation, then run on hardware
            • Older generation Xilinx Vertex 7 (trigger work) on hand.
            • No Aria-10
          • We need to do the work to set up the data piping parts also...
            • Need to work with AD people on how to interface with relevant hardware
              • Talk to Brian about this when he comes back
    • For long term board questions
      • Will be either Xilinx or Aria-10, almost certainly.
        • Depends on what AD wants on their board
        • Aria-Stratix is the right "family"
        • Putting it into the system and laying out a new board will take a lot of time
          • PCB design work takes time
            • 3-6 months (then a couple of months until delivery)
              • What is stopping us from doing this work?
              • Need the NN?
                • Biggest board possible is ~20k
              • We have lots of time (on board), so maybe don't need a huge board?
              • Need to estimate inputs much more clearly - what is the bandwidth?
            • How much of the board is already designed?
              • Are we just swapping the FPGA?
              • Or is it a major update? Kiyomi thinks we don't have a board - starting from scratch.
          • Don't need the FPGA before we start to design the board, just need to know how big of an FPGA we want to use.
          • Some chips are bandwidth optimized, some are resource optimized
      • Xilinx-Altera question
        • Xilinx roadblocks
        • Altera is a distraction for the CMS work
          • But might be useful for HLS4ML
          • Is useful for the tool though to be able to work on Xilinx and Altera (and ATLAS might Altera)
  • Algorithms
    • Need to work on further evaluation of TF-Agents - haven't done much here...

Current Action Items

Everyone

• Everyone will send info to Gabe on how much they plan on charging the grant. - only Kiyomi has done this, for FY 20
  • Nhan will charge 0 in FY 19

Athula

• Thinking about monitoring applications for beams.
• Also thinking about robotics for Bill.

Bill

Brian

• Need to add some stuff to datalogger: in particular, the modifications made to I-star-suite at each cycle by the current system
• Brian wrote an "emulator" that sits in a webpage, will send the url

Gabe

• Gabe will look at Brian's emulator, think about RL agent

Jason

• Jason will begin investigating how to query the data-logger to produce numpy/hdf5 record files for training
• Jason will also work on attaching a PC to the DAQ Brian plans on installing for logging the DAC program output, and on data transfer.

Javier

Kiyomi

Nhan

Retired action items

• Gabe will set up a private channel in the HEPMLSlack
• Javier will send an example of how to get the HLS4ML Quartus model running to the list (it is on the wiki)