Quartus Synthesis Flow Improvement

[bo3z]

Description

📝 Improves the Quartus synthesis flow with more logging, storing resource usage and latency results to files and more robust compilation flags

Type of change

• New feature (non-breaking change which adds functionality)

Tests

📝 A few models were synthesized, in order to verify more logging and the presence of files containing synthesis results.

• I have read the guidelines for contributing.
• I have commented my code, particularly in hard-to-understand areas.
• I have made corresponding changes to the documentation.
• My changes generate no new warnings.
• I have added tests that prove my fix is effective or that my feature works.

This PR attempts to do three things in the Quartus synthesis flow:

1. Add a variable level of logging during HLS synthesis, which allows the user to see the exact stage of HLS synthesis, alongside any warnings, intermediate fails, reasons of failure etc.
2. Write HLS synthesis results (resource usage and timing analysis) to a text file, so these can be reused later. Also, a common issue with Quartus synthesis is an exception encountered when reading verification results (latency and ii), which are obtained by running the binary produced by HLS synthesis. If i++ is not available on the host system natively (such as when it is installed in a container, e.g. singularity), running the binary from hls4ml will throw an exception after which the execution of the entire program halts, because verification results are not obtained. This PR addresses this problem by placing the verification inside a try-catch clause as well as providing clear instructions why an exception is encountered.
3. Adds a flag to HLS synthesis to continue compiling if a large area is estimated. Sometimes, the HLS compiler overestimate the resources needed, and fails compilation. Therefore, we allow the compilation to continue (even if it can't fit on the desired FPGA) to perform some analysis. This is a configurable flag and not used by default.