Updated the reduce function to no longer making unnecessary copies - …

[anders-wind]

…saving a memory usage of NlogN. Also making it C++ standard compliant by removing a zero-sized array

This solves: #300

[anders-wind]

I dont have access to a linux machine currently, but I will try to get @KOVI89alipes to run the code.
Do you have some CI actions set up to try some of these things?

[vloncar]

I am running some CI tests on this (the server was down before). We'll see if anything regressed.

[anders-wind]

Looks like CI checks out :) Is there anything you would like us to try manually?

[thesps]

Indeed, the KERAS_3layer performance is unchanged.

I made this standalone test as well, and everything looks good: identical resources, latency, II, and numerical performance with the old and new version.

Is there anything you would like us to try manually?

Given this started as a solution to #300, we should make sure this actually works on Windows. It would be good if you or @KOVI89alipes can check that.

And as @vloncar says we need to check that a model using Pooling and io_stream is unaffected. The dummy model in #299 should do the trick. I'll use it to test your PR as well as that one.

saving a memory usage of NlogN.

FYI this isn't really a factor in evaluating this: the axes of performance are FPGA resource consumption, latency, throughput (II) and numerical accuracy. On those counts the new version is identical to the old - which is good, and expected.

[thesps]

And as @vloncar says we need to check that a model using Pooling and io_stream is unaffected. The dummy model in #299 should do the trick. I'll use it to test your PR as well as that one.

I've done this. Again, looks good: no change to any of the metrics with the new vs old reduce function.

So now I think we just need the confirmation that it does compile on Windows.

[anders-wind]

FYI this isn't really a factor in evaluating this: the axes of performance are FPGA resource consumption, latency, throughput (II) and numerical accuracy. On those counts the new version is identical to the old - which is good, and expected.

Okay - I have very limited knowledge about FPGA design and code generation. But good to hear that the generated code is atleast identical.

[KOVI89alipes]

I checked this fix, it compiles both in GCC10.1 and MSVC(VS2017) with no extra warning

[thesps]

And how about in Vivado HLS on Windows? It needs to work on whichever compilers they supply

[KOVI89alipes]

Vivado 2020.1
Windows 10

Both CSim and HLS synthesis passed