bugfix: fix esp32c6eco1 fosc calibration cycles during sleep

espressif · May 4, 2023 · dd4d1bb · dd4d1bb
1 parent cac7a5c
commit dd4d1bb
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Showing 8 changed files with 53 additions and 1 deletion.
diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig
@@ -3,6 +3,15 @@ menu "Hardware Settings"
     menu "Chip revision"
         # Insert chip-specific HW config
         orsource "./port/$IDF_TARGET/Kconfig.hw_support"
+
+        config ESP_REV_NEW_CHIP_TEST
+            bool "Internal test mode"
+            depends on IDF_CI_BUILD
+            default n
+            help
+                For internal chip testing, a small number of new versions chips didn't
+                update the version field in eFuse, you can enable this option to force the
+                software recognize the chip version based on the rev selected in menuconfig.
     endmenu
 
     orsource "./port/$IDF_TARGET/Kconfig.spiram"

diff --git a/components/esp_hw_support/port/esp32c6/Kconfig.hw_support b/components/esp_hw_support/port/esp32c6/Kconfig.hw_support
@@ -11,11 +11,14 @@ choice ESP32C6_REV_MIN
 
     config ESP32C6_REV_MIN_0
         bool "Rev v0.0"
+    config ESP32C6_REV_MIN_1
+        bool "Rev v0.1 (ECO1)"
 endchoice
 
 config ESP32C6_REV_MIN_FULL
     int
     default 0 if ESP32C6_REV_MIN_0
+    default 1 if ESP32C6_REV_MIN_1
 
 config ESP_REV_MIN_FULL
     int

diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c
@@ -103,6 +103,15 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
                && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
     }
 
+    /*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
+      So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
+      avoid excessive calibration time.*/
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
+        if (cal_clk == RTC_CAL_RC_FAST) {
+            slowclk_cycles = slowclk_cycles >> 5;
+        }
+    }
+
     /* Prepare calibration */
     REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
     CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);

diff --git a/components/esp_hw_support/port/esp32h2/Kconfig.hw_support b/components/esp_hw_support/port/esp32h2/Kconfig.hw_support
@@ -11,11 +11,17 @@ choice ESP32H2_REV_MIN
 
     config ESP32H2_REV_MIN_0
         bool "Rev v0.0"
+    config ESP32H2_REV_MIN_1
+        bool "Rev v0.1 (ECO1)"
+    config ESP32H2_REV_MIN_2
+        bool "Rev v0.2 (ECO2)"
 endchoice
 
 config ESP32H2_REV_MIN_FULL
     int
     default 0 if ESP32H2_REV_MIN_0
+    default 1 if ESP32H2_REV_MIN_1
+    default 2 if ESP32H2_REV_MIN_2
 
 config ESP_REV_MIN_FULL
     int

diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c
@@ -102,6 +102,15 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
                && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
     }
 
+    /*The Fosc CLK of calibration circuit is divided by 32 for ECO2.
+      So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
+      avoid excessive calibration time.*/
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
+        if (cal_clk == RTC_CAL_RC_FAST) {
+            slowclk_cycles = slowclk_cycles >> 5;
+        }
+    }
+
     /* Prepare calibration */
     REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
     CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);

diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
@@ -99,7 +99,7 @@
 
 // Cycles for RTC Timer clock source (internal oscillator) calibrate
 #define RTC_CLK_SRC_CAL_CYCLES      (10)
-#define FAST_CLK_SRC_CAL_CYCLES     (2000)  /* ~ 127.4 us */
+#define FAST_CLK_SRC_CAL_CYCLES     (2048)  /* ~ 127.4 us */
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (212)

diff --git a/components/hal/esp32c6/efuse_hal.c b/components/hal/esp32c6/efuse_hal.c
@@ -16,12 +16,20 @@
 
 uint32_t efuse_hal_get_major_chip_version(void)
 {
+#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
+    return CONFIG_ESP_REV_MIN_FULL / 100;
+#else
     return efuse_ll_get_chip_wafer_version_major();
+#endif
 }
 
 uint32_t efuse_hal_get_minor_chip_version(void)
 {
+#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
+    return CONFIG_ESP_REV_MIN_FULL % 100;
+#else
     return efuse_ll_get_chip_wafer_version_minor();
+#endif
 }
 
 /******************* eFuse control functions *************************/

diff --git a/components/hal/esp32h2/efuse_hal.c b/components/hal/esp32h2/efuse_hal.c
@@ -16,12 +16,20 @@
 
 uint32_t efuse_hal_get_major_chip_version(void)
 {
+#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
+    return CONFIG_ESP_REV_MIN_FULL / 100;
+#else
     return efuse_ll_get_chip_wafer_version_major();
+#endif
 }
 
 uint32_t efuse_hal_get_minor_chip_version(void)
 {
+#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
+    return CONFIG_ESP_REV_MIN_FULL % 100;
+#else
     return efuse_ll_get_chip_wafer_version_minor();
+#endif
 }
 
 /******************* eFuse control functions *************************/