feat(mbedtls): Add config for interrupt priority in AES and RSA(MPI)

espressif · Oct 12, 2023 · cf4a7bb · cf4a7bb
1 parent a9f7579
commit cf4a7bb
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Showing 4 changed files with 36 additions and 2 deletions.
diff --git a/components/esp_hw_support/include/esp_intr_alloc.h b/components/esp_hw_support/include/esp_intr_alloc.h
@@ -300,6 +300,15 @@ static inline int esp_intr_flags_to_level(int flags)
     return __builtin_ffs((flags & ESP_INTR_FLAG_LEVELMASK) >> 1);
 }
 
+/**
+ * @brief Get the interrupt flags from the supplied level (priority)
+ * @param level The interrupt priority level
+ */
+static inline int esp_intr_level_to_flags(int level)
+{
+    return (level > 0) ? (1 << level) & ESP_INTR_FLAG_LEVELMASK : 0;
+}
+
 /**
  * @brief Dump the status of allocated interrupts
  * @param stream  The stream to dump to, if NULL then stdout is used

diff --git a/components/mbedtls/Kconfig b/components/mbedtls/Kconfig
@@ -391,6 +391,17 @@ menu "mbedTLS"
             This allows other code to run on the CPU while an AES operation is pending.
             Otherwise the CPU busy-waits.
 
+    config MBEDTLS_AES_INTERRUPT_LEVEL
+        int "AES hardware interrupt level"
+        default 0
+        depends on MBEDTLS_AES_USE_INTERRUPT
+        range 0 3
+        help
+            This config helps to set the interrupt priority level for the AES peripheral.
+            Value 0 (default) means that there is no preference regarding the interrupt
+            priority level and any level from 1 to 3 can be selected (based on the availability).
+            Note: Higher value indicates high interrupt priority.
+
     config MBEDTLS_HARDWARE_GCM
         bool "Enable partially hardware accelerated GCM"
         depends on SOC_AES_SUPPORT_GCM && MBEDTLS_HARDWARE_AES
@@ -425,6 +436,17 @@ menu "mbedTLS"
             This allows other code to run on the CPU while an MPI operation is pending.
             Otherwise the CPU busy-waits.
 
+    config MBEDTLS_MPI_INTERRUPT_LEVEL
+        int "MPI hardware interrupt level"
+        default 0
+        depends on MBEDTLS_MPI_USE_INTERRUPT
+        range 0 3
+        help
+            This config helps to set the interrupt priority level for the MPI peripheral.
+            Value 0 (default) means that there is no preference regarding the interrupt
+            priority level and any level from 1 to 3 can be selected (based on the availability).
+            Note: Higher value indicates high interrupt priority.
+
     config MBEDTLS_HARDWARE_SHA
         bool "Enable hardware SHA acceleration"
         default y

diff --git a/components/mbedtls/port/aes/dma/esp_aes.c b/components/mbedtls/port/aes/dma/esp_aes.c
@@ -188,8 +188,9 @@ static esp_err_t esp_aes_isr_initialise( void )
             ESP_LOGE(TAG, "Failed to create intr semaphore");
             return ESP_FAIL;
         }
+        const int isr_flags = esp_intr_level_to_flags(CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL);
 
-        esp_err_t ret = esp_intr_alloc(ETS_AES_INTR_SOURCE, 0, esp_aes_complete_isr, NULL, NULL);
+        esp_err_t ret = esp_intr_alloc(ETS_AES_INTR_SOURCE, isr_flags, esp_aes_complete_isr, NULL, NULL);
         if (ret != ESP_OK) {
             return ret;
         }

diff --git a/components/mbedtls/port/bignum/esp_bignum.c b/components/mbedtls/port/bignum/esp_bignum.c
@@ -85,7 +85,9 @@ static esp_err_t esp_mpi_isr_initialise(void)
             return ESP_FAIL;
         }
 
-        esp_intr_alloc(ETS_RSA_INTR_SOURCE, 0, esp_mpi_complete_isr, NULL, NULL);
+        const int isr_flags = esp_intr_level_to_flags(CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL);
+
+        esp_intr_alloc(ETS_RSA_INTR_SOURCE, isr_flags, esp_mpi_complete_isr, NULL, NULL);
     }
 
     /* MPI is clocked proportionally to CPU clock, take power management lock */