Merge branch 'contrib/github_pr_12481' into 'master'

Many places in the ESP_SYSTEM are using CONFIG_FREERTOS_UNICORE instead of CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE (GitHub PR)

Closes IDFGH-11333

See merge request espressif/esp-idf!27435

components/app_trace/Kconfig

@@ -231,7 +231,7 @@ menu "Application Level Tracing"
 
         choice APPTRACE_SV_CPU
             prompt "CPU to trace"
-            depends on APPTRACE_SV_DEST_UART && !FREERTOS_UNICORE
+            depends on APPTRACE_SV_DEST_UART && !ESP_SYSTEM_SINGLE_CORE_MODE
             default APPTRACE_SV_DEST_CPU_0
             help
                 Define the CPU to trace by SystemView.
@@ -252,16 +252,16 @@ menu "Application Level Tracing"
         choice APPTRACE_SV_TS_SOURCE
             prompt "Timer to use as timestamp source"
             depends on APPTRACE_SV_ENABLE
-            default APPTRACE_SV_TS_SOURCE_CCOUNT if FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
-            default APPTRACE_SV_TS_SOURCE_GPTIMER if !FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
+            default APPTRACE_SV_TS_SOURCE_CCOUNT if ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
+            default APPTRACE_SV_TS_SOURCE_GPTIMER if !ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
             default APPTRACE_SV_TS_SOURCE_ESP_TIMER if PM_ENABLE || IDF_TARGET_ESP32C3
             help
                 SystemView needs to use a hardware timer as the source of timestamps
                 when tracing. This option selects the timer for it.
 
             config APPTRACE_SV_TS_SOURCE_CCOUNT
                 bool "CPU cycle counter (CCOUNT)"
-                depends on FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
+                depends on ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
 
             config APPTRACE_SV_TS_SOURCE_GPTIMER
                 bool "General Purpose Timer (Timer Group)"

components/app_trace/port/xtensa/port.c

@@ -298,7 +298,7 @@ static inline void esp_apptrace_trax_memory_enable(void)
 #if CONFIG_IDF_TARGET_ESP32
         /* Enable trace memory on PRO CPU */
         DPORT_WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M);
-#if CONFIG_FREERTOS_UNICORE == 0
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE == 0
         /* Enable trace memory on APP CPU */
         DPORT_WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M);
 #endif

components/app_trace/sys_view/esp/SEGGER_RTT_esp.c

@@ -35,7 +35,7 @@ static uint8_t s_down_buf[SYSVIEW_DOWN_BUF_SIZE];
 #if CONFIG_APPTRACE_SV_DEST_UART
 
 #define ESP_APPTRACE_DEST_SYSVIEW ESP_APPTRACE_DEST_UART
-#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_FREERTOS_UNICORE
+#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #define APPTRACE_SV_DEST_CPU 0
 #else
 #define APPTRACE_SV_DEST_CPU 1

components/bootloader_support/include/bootloader_memory_utils.h

@@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) {
  */
 __attribute__((always_inline))
 inline static bool esp_ptr_in_iram(const void *p) {
-#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE
+#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
 #else
     return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);

components/bootloader_support/src/bootloader_init.c

@@ -103,7 +103,7 @@ void bootloader_print_banner(void)
 #endif
     }
 
-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #if (SOC_CPU_CORES_NUM > 1)
     ESP_EARLY_LOGW(TAG, "Unicore bootloader");
 #endif

components/bootloader_support/src/bootloader_utility.c

@@ -884,7 +884,7 @@ static void set_cache_and_start_app(
     bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size);
     cache_ll_l1_enable_bus(0, bus_mask);
 
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size);
     cache_ll_l1_enable_bus(1, bus_mask);
     bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size);

components/bootloader_support/src/esp32/bootloader_esp32.c

@@ -44,15 +44,15 @@ static void bootloader_reset_mmu(void)
 {
     /* completely reset MMU in case serial bootloader was running */
     Cache_Read_Disable(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     Cache_Read_Disable(1);
 #endif
     Cache_Flush(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     Cache_Flush(1);
 #endif
     mmu_init(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
         necessary to work around a hardware bug. */
     DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
@@ -63,7 +63,7 @@ static void bootloader_reset_mmu(void)
     /* normal ROM boot exits with DROM0 cache unmasked,
         but serial bootloader exits with it masked. */
     DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
 #endif
 }
@@ -104,7 +104,7 @@ static void wdt_reset_info_dump(int cpu)
         lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
         lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
     } else {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
         stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
         pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
         inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
@@ -154,7 +154,7 @@ static void bootloader_check_wdt_reset(void)
     if (wdt_rst) {
         // if reset by WDT dump info from trace port
         wdt_reset_info_dump(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
         wdt_reset_info_dump(1);
 #endif
     }

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -72,7 +72,7 @@ static void bootloader_check_wdt_reset(void)
     if (wdt_rst) {
         // if reset by WDT dump info from trace port
         wdt_reset_info_dump(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
         wdt_reset_info_dump(1);
 #endif
     }

components/bootloader_support/src/esp32s3/bootloader_esp32s3.c

@@ -70,7 +70,7 @@ static void wdt_reset_info_dump(int cpu)
         lsaddr  = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG);
         lsdata  = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG);
     } else {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
         inst    = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG);
         dstat   = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG);
         data    = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG);
@@ -115,7 +115,7 @@ static void bootloader_check_wdt_reset(void)
     if (wdt_rst) {
         // if reset by WDT dump info from trace port
         wdt_reset_info_dump(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
         wdt_reset_info_dump(1);
 #endif
     }

components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c

@@ -96,13 +96,13 @@ void esp_gdbstub_init_dports(void)
 
 #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
 
-#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
 static bool stall_started = false;
 #endif
 
 void esp_gdbstub_stall_other_cpus_start(void)
 {
-#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
     if (stall_started == false) {
         esp_ipc_isr_stall_other_cpu();
         stall_started = true;
@@ -112,7 +112,7 @@ void esp_gdbstub_stall_other_cpus_start(void)
 
 void esp_gdbstub_stall_other_cpus_end(void)
 {
-#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
     if (stall_started == true) {
         esp_ipc_isr_release_other_cpu();
         stall_started = false;
@@ -142,7 +142,7 @@ void esp_gdbstub_do_step(esp_gdbstub_frame_t *frame)
 
 void esp_gdbstub_trigger_cpu(void)
 {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     if (0 == esp_cpu_get_core_id()) {
         esp_crosscore_int_send_gdb_call(1);
     } else {

components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c

@@ -132,7 +132,7 @@ void esp_gdbstub_init_dports(void)
 {
 }
 
-#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
 static bool stall_started = false;
 #endif
 
@@ -141,7 +141,7 @@ static bool stall_started = false;
  * */
 void esp_gdbstub_stall_other_cpus_start(void)
 {
-#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
     if (stall_started == false) {
         esp_ipc_isr_stall_other_cpu();
         stall_started = true;
@@ -154,7 +154,7 @@ void esp_gdbstub_stall_other_cpus_start(void)
  * */
 void esp_gdbstub_stall_other_cpus_end(void)
 {
-#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
     if (stall_started == true) {
         esp_ipc_isr_release_other_cpu();
         stall_started = false;
@@ -193,7 +193,7 @@ void esp_gdbstub_do_step( esp_gdbstub_frame_t *frame)
  * */
 void esp_gdbstub_trigger_cpu(void)
 {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     if (0 == esp_cpu_get_core_id()) {
         esp_crosscore_int_send_gdb_call(1);
     } else {

components/esp_hw_support/include/dport_access.h

@@ -13,7 +13,7 @@
 extern "C" {
 #endif
 
-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND
 #define DPORT_STALL_OTHER_CPU_START()
 #define DPORT_STALL_OTHER_CPU_END()
 #else

components/esp_hw_support/include/esp_memory_utils.h

@@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) {
  */
 __attribute__((always_inline))
 inline static bool esp_ptr_in_iram(const void *p) {
-#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE
+#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
 #else
     return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
@@ -230,7 +230,7 @@ inline static bool esp_ptr_executable(const void *p)
     return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
         || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
         || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
-#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
+#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE)
         || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
 #endif
 #if SOC_RTC_FAST_MEM_SUPPORTED

components/esp_hw_support/include/spinlock.h

@@ -51,7 +51,7 @@ typedef struct {
 static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t *lock)
 {
     assert(lock);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     lock->owner = SPINLOCK_FREE;
     lock->count = 0;
 #endif
@@ -73,7 +73,7 @@ static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t
  */
 static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *lock, int32_t timeout)
 {
-#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
     uint32_t irq_status;
     uint32_t core_owner_id, other_core_owner_id;
     bool lock_set;
@@ -151,7 +151,7 @@ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *l
 #endif
     return lock_set;
 
-#else  // !CONFIG_FREERTOS_UNICORE
+#else  // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     return true;
 #endif
 }
@@ -171,7 +171,7 @@ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *l
  */
 static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *lock)
 {
-#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
     uint32_t irq_status;
     uint32_t core_owner_id;
 
@@ -198,7 +198,7 @@ static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *l
 #else
     rv_utils_restore_intlevel(irq_status);
 #endif  //#if __XTENSA__
-#endif  //#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
+#endif  //#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
 }
 
 #ifdef __cplusplus

components/esp_mm/cache_esp32.c

@@ -27,7 +27,7 @@ void cache_sync(void)
     }
 
     s_cache_drv.cache_flush(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     s_cache_drv.cache_flush(1);
-#endif // !CONFIG_FREERTOS_UNICORE
+#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 }

components/esp_mm/esp_mmu_map.c

@@ -402,9 +402,9 @@ FORCE_INLINE_ATTR uint32_t s_mapping_operation(mmu_target_t target, uint32_t vad
 
     mmu_hal_map_region(0, target, vaddr_start, paddr_start, size, &actual_mapped_len);
 #if (SOC_MMU_PERIPH_NUM == 2)
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     mmu_hal_map_region(1, target, vaddr_start, paddr_start, size, &actual_mapped_len);
-#endif //  #if !CONFIG_FREERTOS_UNICORE
+#endif //  #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #endif //  #if (SOC_MMU_PERIPH_NUM == 2)
 
     return actual_mapped_len;
@@ -424,7 +424,7 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_mapping(mmu_target_t target, uint32_t v
 
     cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size);
     cache_ll_l1_enable_bus(0, bus_mask);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size);
     cache_ll_l1_enable_bus(1, bus_mask);
 #endif
@@ -602,9 +602,9 @@ FORCE_INLINE_ATTR void s_unmapping_operation(uint32_t vaddr_start, uint32_t size
 {
     mmu_hal_unmap_region(0, vaddr_start, size);
 #if (SOC_MMU_PERIPH_NUM == 2)
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     mmu_hal_unmap_region(1, vaddr_start, size);
-#endif //  #if !CONFIG_FREERTOS_UNICORE
+#endif //  #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #endif //  #if (SOC_MMU_PERIPH_NUM == 2)
 }
 #endif

components/esp_psram/esp32/esp_psram_extram_cache.c

@@ -9,7 +9,7 @@
 #include "esp_psram.h"
 #include "esp_private/esp_psram_extram.h"
 
-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
 #else
 #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
@@ -38,7 +38,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
         cache_was_disabled |= (1 << 0);
         DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
     }
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) == 0) {
         cache_was_disabled |= (1 << 1);
         DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
@@ -70,7 +70,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
         while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
         DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
     }
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     if (cache_was_disabled & (1 << 1)) {
         while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
         DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);

components/esp_psram/esp32/esp_psram_impl_quad.c

@@ -201,7 +201,7 @@ typedef enum {
     PSRAM_VADDR_MODE_EVENODD,    ///< App and pro CPU share external RAM caches: pro CPU does even 32yte ranges, app does odd ones.
 } psram_vaddr_mode_t;
 
-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
 #else
 #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH

components/esp_psram/esp32s2/esp_psram_impl_quad.c

@@ -531,7 +531,7 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
     SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
                       SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache :  40m--+1dummy,80m--+2dummy
 
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT);
     DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT);
     if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {