Merge branch 'change/delete_not_used_mmu_macros' into 'master'

mm: delete not used mmu macros and added soc_ prefix

Closes IDF-7686

See merge request espressif/esp-idf!25663

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -151,9 +151,9 @@ static const char *TAG = "bootloader_flash";
 #define MMU_BLOCK0_VADDR  SOC_DROM_LOW
 #if CONFIG_IDF_TARGET_ESP32P4
 //TODO: IDF-7918
-#define MMAP_MMU_SIZE     (DRAM_FLASH_ADDRESS_HIGH - DRAM_FLASH_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
+#define MMAP_MMU_SIZE     (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_DRAM_FLASH_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
 #else
-#define MMAP_MMU_SIZE     (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
+#define MMAP_MMU_SIZE     (SOC_DRAM0_CACHE_ADDRESS_HIGH - SOC_DRAM0_CACHE_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
 #endif
 #define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE - SPI_FLASH_MMU_PAGE_SIZE)
 #define FLASH_READ_VADDR MMU_BLOCK63_VADDR

components/esp_mm/port/esp32/ext_mem_layout.c

@@ -18,23 +18,23 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_32BIT,
     },
     [1] = {
         .start = SOC_MMU_DROM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DROM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DROM0_LINEAR),
         .bus_id = CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
     },
     [2] = {
         .start = SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
         .bus_id = CACHE_BUS_DBUS1,
         .targets = MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32c2/ext_mem_layout.c

@@ -17,7 +17,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32c3/ext_mem_layout.c

@@ -17,7 +17,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32c6/ext_mem_layout.c

@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32h2/ext_mem_layout.c

@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32p4/ext_mem_layout.c

@@ -18,15 +18,15 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_FLASH_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_FLASH_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_FLASH_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
     },
     [1] = {
         .start = SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_PSRAM_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_PSRAM_LINEAR),
         .bus_id = CACHE_BUS_IBUS1 | CACHE_BUS_DBUS1,
         .targets = MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32s2/ext_mem_layout.c

@@ -18,39 +18,39 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_32BIT,
     },
     [1] = {
         .start = SOC_MMU_DROM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DROM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DROM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS2,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
     },
     [2] = {
         .start = SOC_MMU_DPORT_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DPORT_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DPORT_LINEAR),
         .bus_id = CACHE_BUS_DBUS2,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT,
     },
     [3] = {
         .start = SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
         .bus_id = CACHE_BUS_DBUS1,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
     },
     [4] = {
         .start = SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DRAM0_LINEAR),
         .bus_id = CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32s3/ext_mem_layout.c

@@ -17,7 +17,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_psram/mmu_psram_flash.c

@@ -73,10 +73,10 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
     instruction_flash_page_info_init(page_id);
 
 #if CONFIG_IDF_TARGET_ESP32S2
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, IRAM0_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, IRAM1_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, SOC_IRAM0_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, SOC_IRAM1_ADDRESS_LOW, page_id, &page0_page);
 #elif CONFIG_IDF_TARGET_ESP32S3
-    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, IRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, SOC_IRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
 #endif
     ESP_EARLY_LOGV(TAG, "after copy instruction, page_id is %d", page_id);
     ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM");
@@ -118,12 +118,12 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
     rodata_flash_page_info_init(page_id);
 
 #if CONFIG_IDF_TARGET_ESP32S2
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, DROM0_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, DRAM0_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, DRAM1_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, DPORT_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, SOC_DROM0_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, SOC_DRAM0_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, SOC_DRAM1_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, SOC_DPORT_ADDRESS_LOW, page_id, &page0_page);
 #elif CONFIG_IDF_TARGET_ESP32S3
-    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, DRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, SOC_DRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
 #endif
 
     ESP_EARLY_LOGV(TAG, "after copy rodata, page_id is %d", page_id);
@@ -162,13 +162,13 @@ void instruction_flash_page_info_init(uint32_t psram_start_physical_page)
 {
 #if CONFIG_IDF_TARGET_ESP32S2
     uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
-    uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE;
+    uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & SOC_MMU_VADDR_MASK) / MMU_PAGE_SIZE;
     instr_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START))[instr_mmu_offset];
 #elif CONFIG_IDF_TARGET_ESP32S3
     uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
     instr_start_page = *((volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START));
 #endif
-    instr_start_page &= MMU_VALID_VAL_MASK;
+    instr_start_page &= SOC_MMU_VALID_VAL_MASK;
     instr_end_page = instr_start_page + instr_page_cnt - 1;
     instr_flash2spiram_offs = instr_start_page - psram_start_physical_page;
     instruction_in_spiram = 1;
@@ -215,13 +215,13 @@ void rodata_flash_page_info_init(uint32_t psram_start_physical_page)
 {
 #if CONFIG_IDF_TARGET_ESP32S2
     uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
-    uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE;
+    uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & SOC_MMU_VADDR_MASK) / MMU_PAGE_SIZE;
     rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_mmu_offset];
 #elif CONFIG_IDF_TARGET_ESP32S3
     uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
     rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START);
 #endif
-    rodata_start_page &= MMU_VALID_VAL_MASK;
+    rodata_start_page &= SOC_MMU_VALID_VAL_MASK;
     rodata_end_page = rodata_start_page + rodata_page_cnt - 1;
     rodata_flash2spiram_offs = rodata_start_page - psram_start_physical_page;
     rodata_in_spiram = 1;

components/esp_rom/include/esp32c6/rom/cache.h

@@ -602,7 +602,7 @@ uint32_t Cache_Get_DROM_MMU_End(void);
 void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
 
 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \
-    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
+    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
 
 #ifdef __cplusplus
 }

components/esp_rom/include/esp32h2/rom/cache.h

@@ -605,7 +605,7 @@ uint32_t Cache_Get_DROM_MMU_End(void);
 void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
 
 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \
-    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
+    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
 
 #ifdef __cplusplus
 }

components/esp_rom/include/esp32s3/rom/cache.h

@@ -224,7 +224,7 @@ void Cache_MMU_Init(void);
   * @brief Set ICache mmu mapping.
   *        Please do not call this function in your SDK application.
   *
-  * @param  uint32_t ext_ram : MMU_ACCESS_FLASH for flash, MMU_ACCESS_SPIRAM for spiram, MMU_INVALID for invalid.
+  * @param  uint32_t ext_ram : SOC_MMU_ACCESS_FLASH for flash, SOC_MMU_ACCESS_SPIRAM for spiram, SOC_MMU_INVALID for invalid.
   *
   * @param  uint32_t vaddr : virtual address in CPU address space.
   *                              Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
@@ -251,7 +251,7 @@ int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,  uint32
   * @brief Set DCache mmu mapping.
   *        Please do not call this function in your SDK application.
   *
-  * @param  uint32_t ext_ram : MMU_ACCESS_FLASH for flash, MMU_ACCESS_SPIRAM for spiram, MMU_INVALID for invalid.
+  * @param  uint32_t ext_ram : SOC_MMU_ACCESS_FLASH for flash, SOC_MMU_ACCESS_SPIRAM for spiram, SOC_MMU_INVALID for invalid.
   *
   * @param  uint32_t vaddr : virtual address in CPU address space.
   *                              Can be DRam0, DRam1, DRom0, DPort and AHB buses address.

components/esp_system/port/arch/xtensa/panic_arch.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -200,7 +200,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("Icache reject error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");
@@ -235,7 +235,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("Dcache reject error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");
@@ -245,7 +245,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("MMU entry fault error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");
@@ -347,7 +347,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("MMU entry fault error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");

components/esp_system/port/cpu_start.c

@@ -504,7 +504,7 @@ void IRAM_ATTR call_start_cpu0(void)
         esp_restart();
     }
 
-#if CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
+#if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 #if CONFIG_APP_BUILD_TYPE_ELF_RAM
     // For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data
     // are all in internal RAM. If the RAM loadable ELF has any requirement to memory map the
@@ -521,7 +521,7 @@ void IRAM_ATTR call_start_cpu0(void)
 
     /* Configure the Cache MMU size for instruction and rodata in flash. */
     Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
-#endif // CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
+#endif // ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 
 #if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
     bool efuse_opflash_en = efuse_ll_get_flash_type();

components/hal/esp32/include/hal/cache_ll.h

@@ -98,22 +98,22 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     cache_bus_mask_t mask = 0;
 
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IROM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_HIGH) {
         HAL_ASSERT(false);      //out of range
-    } else if (vaddr_start >= IROM0_CACHE_ADDRESS_LOW) {
+    } else if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS2;
-    } else if (vaddr_start >= IRAM1_CACHE_ADDRESS_LOW) {
+    } else if (vaddr_start >= SOC_IRAM1_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS1;
-        mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
-    } else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {
+        mask |= (vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
+    } else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS0;
-        mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
-        mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
-    } else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+        mask |= (vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
+        mask |= (vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
+    } else if (vaddr_start >= SOC_DRAM1_CACHE_ADDRESS_LOW) {
+        HAL_ASSERT(vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS1;
-    } else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+    } else if (vaddr_start >= SOC_DROM0_CACHE_ADDRESS_LOW) {
+        HAL_ASSERT(vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(false);