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Merge branch 'feature/freertos-10.5.1-added-base-riscv-porting-layer'…
… into 'master' feat(freertos): added base risc-v porting layer to 10.5.1 See merge request espressif/esp-idf!24773
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73
...Kernel-V10.5.1/portable/riscv/include/freertos/freertos_risc_v_chip_specific_extensions.h
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| /* | ||
| * FreeRTOS Kernel V10.5.1 (ESP-IDF SMP modified) | ||
| * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. | ||
| * | ||
| * SPDX-FileCopyrightText: 2021 Amazon.com, Inc. or its affiliates | ||
| * | ||
| * SPDX-License-Identifier: MIT | ||
| * | ||
| * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD | ||
| * | ||
| * Permission is hereby granted, free of charge, to any person obtaining a copy of | ||
| * this software and associated documentation files (the "Software"), to deal in | ||
| * the Software without restriction, including without limitation the rights to | ||
| * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of | ||
| * the Software, and to permit persons to whom the Software is furnished to do so, | ||
| * subject to the following conditions: | ||
| * | ||
| * The above copyright notice and this permission notice shall be included in all | ||
| * copies or substantial portions of the Software. | ||
| * | ||
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS | ||
| * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR | ||
| * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER | ||
| * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
| * | ||
| * https://www.FreeRTOS.org | ||
| * https://github.com/FreeRTOS | ||
| * | ||
| */ | ||
|
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| /* | ||
| * The FreeRTOS kernel's RISC-V port is split between the the code that is | ||
| * common across all currently supported RISC-V chips (implementations of the | ||
| * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: | ||
| * | ||
| * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that | ||
| * is common to all currently supported RISC-V chips. There is only one | ||
| * portASM.S file because the same file is built for all RISC-V target chips. | ||
| * | ||
| * + Header files called freertos_risc_v_chip_specific_extensions.h contain the | ||
| * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V | ||
| * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files | ||
| * as there are multiple RISC-V chip implementations. | ||
| * | ||
| * !!!NOTE!!! | ||
| * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h | ||
| * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the | ||
| * compiler's!) include path. For example, if the chip in use includes a core | ||
| * local interrupter (CLINT) and does not include any chip specific register | ||
| * extensions then add the path below to the assembler's include path: | ||
| * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions | ||
| * | ||
| */ | ||
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| #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ | ||
| #define __FREERTOS_RISC_V_EXTENSIONS_H__ | ||
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| #define portasmHAS_SIFIVE_CLINT 0 | ||
| #define portasmHAS_MTIME 0 | ||
| #define portasmADDITIONAL_CONTEXT_SIZE 0 | ||
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| .macro portasmSAVE_ADDITIONAL_REGISTERS | ||
| /* No additional registers to save, so this macro does nothing. */ | ||
| .endm | ||
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| .macro portasmRESTORE_ADDITIONAL_REGISTERS | ||
| /* No additional registers to restore, so this macro does nothing. */ | ||
| .endm | ||
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| #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ |
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components/freertos/FreeRTOS-Kernel-V10.5.1/portable/riscv/include/freertos/portContext.h
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| /* | ||
| * FreeRTOS Kernel V10.5.1 (ESP-IDF SMP modified) | ||
| * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. | ||
| * | ||
| * SPDX-FileCopyrightText: 2021 Amazon.com, Inc. or its affiliates | ||
| * | ||
| * SPDX-License-Identifier: MIT | ||
| * | ||
| * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD | ||
| * | ||
| * Permission is hereby granted, free of charge, to any person obtaining a copy of | ||
| * this software and associated documentation files (the "Software"), to deal in | ||
| * the Software without restriction, including without limitation the rights to | ||
| * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of | ||
| * the Software, and to permit persons to whom the Software is furnished to do so, | ||
| * subject to the following conditions: | ||
| * | ||
| * The above copyright notice and this permission notice shall be included in all | ||
| * copies or substantial portions of the Software. | ||
| * | ||
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS | ||
| * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR | ||
| * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER | ||
| * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
| * | ||
| * https://www.FreeRTOS.org | ||
| * https://github.com/FreeRTOS | ||
| * | ||
| */ | ||
|
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| #ifndef PORTCONTEXT_H | ||
| #define PORTCONTEXT_H | ||
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| #if __riscv_xlen == 64 | ||
| #define portWORD_SIZE 8 | ||
| #define store_x sd | ||
| #define load_x ld | ||
| #elif __riscv_xlen == 32 | ||
| #define store_x sw | ||
| #define load_x lw | ||
| #define portWORD_SIZE 4 | ||
| #else | ||
| #error Assembler did not define __riscv_xlen | ||
| #endif | ||
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| #include "freertos_risc_v_chip_specific_extensions.h" | ||
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| /* Only the standard core registers are stored by default. Any additional | ||
| * registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and | ||
| * portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip | ||
| * specific version of freertos_risc_v_chip_specific_extensions.h. See the | ||
| * notes at the top of portASM.S file. */ | ||
| #ifdef __riscv_32e | ||
| #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) | ||
| #define portCRITICAL_NESTING_OFFSET 13 | ||
| #define portMSTATUS_OFFSET 14 | ||
| #else | ||
| #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) | ||
| #define portCRITICAL_NESTING_OFFSET 29 | ||
| #define portMSTATUS_OFFSET 30 | ||
| #endif | ||
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| /*-----------------------------------------------------------*/ | ||
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| .extern pxCurrentTCB | ||
| .extern xISRStackTop | ||
| .extern xCriticalNesting | ||
| .extern pxCriticalNesting | ||
| /*-----------------------------------------------------------*/ | ||
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| .macro portcontextSAVE_CONTEXT_INTERNAL | ||
| addi sp, sp, -portCONTEXT_SIZE | ||
| store_x x1, 1 * portWORD_SIZE( sp ) | ||
| store_x x5, 2 * portWORD_SIZE( sp ) | ||
| store_x x6, 3 * portWORD_SIZE( sp ) | ||
| store_x x7, 4 * portWORD_SIZE( sp ) | ||
| store_x x8, 5 * portWORD_SIZE( sp ) | ||
| store_x x9, 6 * portWORD_SIZE( sp ) | ||
| store_x x10, 7 * portWORD_SIZE( sp ) | ||
| store_x x11, 8 * portWORD_SIZE( sp ) | ||
| store_x x12, 9 * portWORD_SIZE( sp ) | ||
| store_x x13, 10 * portWORD_SIZE( sp ) | ||
| store_x x14, 11 * portWORD_SIZE( sp ) | ||
| store_x x15, 12 * portWORD_SIZE( sp ) | ||
| #ifndef __riscv_32e | ||
| store_x x16, 13 * portWORD_SIZE( sp ) | ||
| store_x x17, 14 * portWORD_SIZE( sp ) | ||
| store_x x18, 15 * portWORD_SIZE( sp ) | ||
| store_x x19, 16 * portWORD_SIZE( sp ) | ||
| store_x x20, 17 * portWORD_SIZE( sp ) | ||
| store_x x21, 18 * portWORD_SIZE( sp ) | ||
| store_x x22, 19 * portWORD_SIZE( sp ) | ||
| store_x x23, 20 * portWORD_SIZE( sp ) | ||
| store_x x24, 21 * portWORD_SIZE( sp ) | ||
| store_x x25, 22 * portWORD_SIZE( sp ) | ||
| store_x x26, 23 * portWORD_SIZE( sp ) | ||
| store_x x27, 24 * portWORD_SIZE( sp ) | ||
| store_x x28, 25 * portWORD_SIZE( sp ) | ||
| store_x x29, 26 * portWORD_SIZE( sp ) | ||
| store_x x30, 27 * portWORD_SIZE( sp ) | ||
| store_x x31, 28 * portWORD_SIZE( sp ) | ||
| #endif | ||
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| load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ | ||
| store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ | ||
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| csrr t0, mstatus /* Required for MPIE bit. */ | ||
| store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) | ||
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| portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ | ||
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| load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ | ||
| store_x sp, 0( t0 ) /* Write sp to first TCB member. */ | ||
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| .endm | ||
| /*-----------------------------------------------------------*/ | ||
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| .macro portcontextSAVE_EXCEPTION_CONTEXT | ||
| portcontextSAVE_CONTEXT_INTERNAL | ||
| csrr a0, mcause | ||
| csrr a1, mepc | ||
| addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ | ||
| store_x a1, 0( sp ) /* Save updated exception return address. */ | ||
| load_x sp, xISRStackTop /* Switch to ISR stack. */ | ||
| .endm | ||
| /*-----------------------------------------------------------*/ | ||
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| .macro portcontextSAVE_INTERRUPT_CONTEXT | ||
| portcontextSAVE_CONTEXT_INTERNAL | ||
| csrr a0, mcause | ||
| csrr a1, mepc | ||
| store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ | ||
| load_x sp, xISRStackTop /* Switch to ISR stack. */ | ||
| .endm | ||
| /*-----------------------------------------------------------*/ | ||
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| .macro portcontextRESTORE_CONTEXT | ||
| load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ | ||
| load_x sp, 0( t1 ) /* Read sp from first TCB member. */ | ||
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| /* Load mepc with the address of the instruction in the task to run next. */ | ||
| load_x t0, 0( sp ) | ||
| csrw mepc, t0 | ||
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| /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ | ||
| portasmRESTORE_ADDITIONAL_REGISTERS | ||
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| /* Load mstatus with the interrupt enable bits used by the task. */ | ||
| load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) | ||
| csrw mstatus, t0 /* Required for MPIE bit. */ | ||
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| load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ | ||
| load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ | ||
| store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */ | ||
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| load_x x1, 1 * portWORD_SIZE( sp ) | ||
| load_x x5, 2 * portWORD_SIZE( sp ) | ||
| load_x x6, 3 * portWORD_SIZE( sp ) | ||
| load_x x7, 4 * portWORD_SIZE( sp ) | ||
| load_x x8, 5 * portWORD_SIZE( sp ) | ||
| load_x x9, 6 * portWORD_SIZE( sp ) | ||
| load_x x10, 7 * portWORD_SIZE( sp ) | ||
| load_x x11, 8 * portWORD_SIZE( sp ) | ||
| load_x x12, 9 * portWORD_SIZE( sp ) | ||
| load_x x13, 10 * portWORD_SIZE( sp ) | ||
| load_x x14, 11 * portWORD_SIZE( sp ) | ||
| load_x x15, 12 * portWORD_SIZE( sp ) | ||
| #ifndef __riscv_32e | ||
| load_x x16, 13 * portWORD_SIZE( sp ) | ||
| load_x x17, 14 * portWORD_SIZE( sp ) | ||
| load_x x18, 15 * portWORD_SIZE( sp ) | ||
| load_x x19, 16 * portWORD_SIZE( sp ) | ||
| load_x x20, 17 * portWORD_SIZE( sp ) | ||
| load_x x21, 18 * portWORD_SIZE( sp ) | ||
| load_x x22, 19 * portWORD_SIZE( sp ) | ||
| load_x x23, 20 * portWORD_SIZE( sp ) | ||
| load_x x24, 21 * portWORD_SIZE( sp ) | ||
| load_x x25, 22 * portWORD_SIZE( sp ) | ||
| load_x x26, 23 * portWORD_SIZE( sp ) | ||
| load_x x27, 24 * portWORD_SIZE( sp ) | ||
| load_x x28, 25 * portWORD_SIZE( sp ) | ||
| load_x x29, 26 * portWORD_SIZE( sp ) | ||
| load_x x30, 27 * portWORD_SIZE( sp ) | ||
| load_x x31, 28 * portWORD_SIZE( sp ) | ||
| #endif | ||
| addi sp, sp, portCONTEXT_SIZE | ||
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| mret | ||
| .endm | ||
| /*-----------------------------------------------------------*/ | ||
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| #endif /* PORTCONTEXT_H */ |
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