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Merge branch 'bugfix/fix_wrong_mem_caps_in_memory_layout' into 'master'
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fix(heap):  fix the issue on esp32c3 where retention memory was exhausted prematurely and preventing the CPU from powering down

Closes IDF-8236

See merge request espressif/esp-idf!25962
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jack0c committed Oct 12, 2023
2 parents 239bc3b + 5926116 commit 5debc3b
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Showing 11 changed files with 288 additions and 320 deletions.
4 changes: 2 additions & 2 deletions components/heap/heap_caps_init.c
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ void heap_caps_init(void)
for (size_t i = 1; i < num_regions; i++) {
soc_memory_region_t *a = &regions[i - 1];
soc_memory_region_t *b = &regions[i];
if (b->start == (intptr_t)(a->start + a->size) && b->type == a->type ) {
if (b->start == (intptr_t)(a->start + a->size) && b->type == a->type && b->startup_stack == a->startup_stack ) {
a->type = -1;
b->start = a->start;
b->size += a->size;
Expand Down Expand Up @@ -102,7 +102,7 @@ void heap_caps_init(void)
heap->start = region->start;
heap->end = region->start + region->size;
MULTI_HEAP_LOCK_INIT(&heap->heap_mux);
if (type->startup_stack) {
if (region->startup_stack) {
/* Will be registered when OS scheduler starts */
heap->heap = NULL;
} else {
Expand Down
27 changes: 9 additions & 18 deletions components/heap/include/heap_memory_layout.h
Original file line number Diff line number Diff line change
@@ -1,16 +1,8 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at

// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

#pragma once
#include <stdlib.h>
Expand All @@ -29,8 +21,6 @@ extern "C" {
typedef struct {
const char *name; ///< Name of this memory type
uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for this memory type (as a prioritised set)
bool aliased_iram; ///< If true, this is data memory that is is also mapped in IRAM
bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
} soc_memory_type_desc_t;

/* Constant table of tag descriptors for all this SoC's tags */
Expand All @@ -40,10 +30,11 @@ extern const size_t soc_memory_type_count;
/* Region descriptor holds a description for a particular region of memory on a particular SoC.
*/
typedef struct {
intptr_t start; ///< Start address of the region
intptr_t start; ///< Start address of the region
size_t size; ///< Size of the region in bytes
size_t type; ///< Type of the region (index into soc_memory_types array)
intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
size_t type; ///< Type of the region (index into soc_memory_types array)
intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
} soc_memory_region_t;

extern const soc_memory_region_t soc_memory_regions[];
Expand Down
133 changes: 64 additions & 69 deletions components/heap/port/esp32/memory_layout.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -33,34 +33,29 @@ The prioritised capabilities work roughly like this:
- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
- Most other malloc caps only fit in one region anyway.
*/

enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_DIRAM = 1,
SOC_MEMORY_TYPE_IRAM = 2,
SOC_MEMORY_TYPE_SPIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_NUM,
};

const soc_memory_type_desc_t soc_memory_types[] = {
//Type 0: Plain ole D-port RAM
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }},
//Type 1: Plain ole D-port RAM which has an alias on the I-port
//(This DRAM is also the region used by ROM during startup)
{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true},
//(This DRAM is also the region used by ROM during startup, and decrease the allocation priority to avoid MALLOC_CAP_EXEC memory running out too soon)
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }},
//Type 2: IRAM
{ "IRAM", { MALLOC_CAP_INTERNAL|MALLOC_IRAM_CAP, 0, 0 }, false, false},
//Type 3-8: PID 2-7 IRAM
{ "PID2IRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID3IRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID4IRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID5IRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID6IRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID7IRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
//Type 9-14: PID 2-7 DRAM
{ "PID2DRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID3DRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID4DRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
//Type 15: SPI SRAM data
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 16: RTC Fast RAM
{ "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false},
[SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_INTERNAL|MALLOC_IRAM_CAP, 0, 0 }},
//Type 3: SPI SRAM data
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}},
//Type 4: RTC Fast RAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }},
};

const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
Expand All @@ -73,53 +68,53 @@ from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 15, 0}, //SPI SRAM, if available
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
#endif
{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
{ 0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions.
{ 0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
{ 0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
{ 0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
{ 0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
{ 0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
{ 0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
{ 0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
{ 0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
{ 0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
{ 0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
{ 0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
{ 0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
{ 0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
{ 0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
{ 0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
{ 0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
{ 0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
{ 0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
{ 0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ 0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
{ 0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
{ 0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
{ 0x40070000, 0x8000, 2, 0}, //pool 0
{ 0x40078000, 0x8000, 2, 0}, //pool 1
{ 0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
{ 0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
{ 0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
{ 0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
{ 0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
{ 0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
{ 0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
{ 0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
{ 0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
{ 0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
{ 0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
{ 0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
{ 0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
{ 0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
{ 0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
{ 0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
{ 0x3FFAE000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 16 <- used for rom code
{ 0x3FFB0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 15 <- if BT is enabled, used as BT HW shared memory
{ 0x3FFB8000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions.
{ 0x3FFC0000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 0
{ 0x3FFC2000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 1
{ 0x3FFC4000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 2
{ 0x3FFC6000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 3
{ 0x3FFC8000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 4
{ 0x3FFCA000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 5
{ 0x3FFCC000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 6
{ 0x3FFCE000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 7
{ 0x3FFD0000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 8
{ 0x3FFD2000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 9
{ 0x3FFD4000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 10
{ 0x3FFD6000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 11
{ 0x3FFD8000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 12
{ 0x3FFDA000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 13
{ 0x3FFDC000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 14
{ 0x3FFDE000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 15
{ 0x3FFE0000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400BC000,true}, //pool 9 blk 1
{ 0x3FFE4000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400B8000,true}, //pool 9 blk 0
{ 0x3FFE8000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x400B0000,true}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ 0x3FFF0000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x400A8000,true}, //pool 7 <- can be used for MAC dump
{ 0x3FFF8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400A4000,true}, //pool 6 blk 1 <- can be used as trace memory
{ 0x3FFFC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400A0000,true}, //pool 6 blk 0 <- can be used as trace memory
{ 0x40070000, 0x8000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 0
{ 0x40078000, 0x8000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 1
{ 0x40080000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 0
{ 0x40082000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 1
{ 0x40084000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 2
{ 0x40086000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 3
{ 0x40088000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 4
{ 0x4008A000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 5
{ 0x4008C000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 6
{ 0x4008E000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 7
{ 0x40090000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 8
{ 0x40092000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 9
{ 0x40094000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 10
{ 0x40096000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 11
{ 0x40098000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 12
{ 0x4009A000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 13
{ 0x4009C000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 14
{ 0x4009E000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 15
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ SOC_RTC_DRAM_LOW, 0x2000, 16, 0}, //RTC Fast Memory
{ SOC_RTC_DRAM_LOW, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //RTC Fast Memory
#endif
};

Expand Down
23 changes: 8 additions & 15 deletions components/heap/port/esp32c2/memory_layout.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -28,20 +28,15 @@

/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_STACK_DRAM = 0,
SOC_MEMORY_TYPE_DIRAM = 1,
SOC_MEMORY_TYPE_RAM = 0,
SOC_MEMORY_TYPE_NUM,
};

const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 1: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 0: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_RAM] = { "RAM", { MALLOC_CAP_DEFAULT | MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_EXEC, 0, 0 }},
};

#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM

const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);

/**
Expand All @@ -58,16 +53,14 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)

const soc_memory_region_t soc_memory_regions[] = {
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //D/IRAM level2
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level3
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)} //D/IRAM level3 (ROM reserved area)
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40380000, false}, //D/IRAM level1
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40390000, false}, //D/IRAM level2
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_RAM, 0x403A0000, false}, //D/IRAM level3
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END), true} //D/IRAM level3 (ROM reserved area)
};


const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);


extern int _data_start, _heap_start, _iram_start, _iram_end;

/**
Expand Down
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