Merge branch 'fix/unused_interrupts' into 'master'

fix(esp_hw_ ‎support): clear reserved interrupts that are unused or not applicable anymore

Closes IDF-7821 and IDF-9428

See merge request espressif/esp-idf!29639

components/esp_hw_support/include/esp_private/esp_riscv_intr.h

@@ -9,6 +9,37 @@
 
 #if CONFIG_IDF_TARGET_ARCH_RISCV
 
+#if SOC_INT_CLIC_SUPPORTED
+
+/**
+ * @brief Checks whether the given interrupt number is reserved either in the given mask or in the
+ *        _mtvt_table, which contains the routines the CPU will jump to when an interrupt or an exception
+ *        occurs, on RISC-V targets.
+ *
+ * @param intr_num  External interrupt number to check, in range 0~32
+ * @param rsvd_mask Reserved interrupt mask, where bit i is 1 if interrupt i is reserved.
+ *
+ * @returns ESP_CPU_INTR_DESC_FLAG_RESVD if the interrupt is reserved, 0 else
+ */
+static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask)
+{
+    if (rsvd_mask & BIT(intr_num)) {
+        return ESP_CPU_INTR_DESC_FLAG_RESVD;
+    }
+
+    extern intptr_t _mtvt_table[48];
+    extern intptr_t _interrupt_handler;
+
+    /* The first 16 entries of the array are internal interrupt, ignore them  */
+    const intptr_t destination = _mtvt_table[16 + intr_num];
+
+    return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
+}
+
+
+
+#else // !SOC_INT_CLIC_SUPPORTED
+
 #include "esp_cpu.h"
 #include "riscv/instruction_decode.h"
 
@@ -28,14 +59,16 @@ static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask
         return ESP_CPU_INTR_DESC_FLAG_RESVD;
     }
 
-    extern int _vector_table;
+    extern intptr_t _vector_table[32];
     extern int _interrupt_handler;
-    const intptr_t pc = (intptr_t)(&_vector_table + intr_num);
+    const intptr_t pc = (intptr_t) &_vector_table[intr_num];
 
     /* JAL instructions are relative to the PC they are executed from. */
     const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc);
 
     return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
 }
 
+#endif // SOC_INT_CLIC_SUPPORTED
+
 #endif // CONFIG_IDF_TARGET_ARCH_RISCV

components/esp_hw_support/intr_alloc.c

@@ -630,7 +630,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
         esp_intr_disable(ret);
     }
 
-#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
+#if SOC_CPU_HAS_FLEXIBLE_INTC
     //Extract the level from the interrupt passed flags
     int level = esp_intr_flags_to_level(flags);
     esp_cpu_intr_set_priority(intr, level);
@@ -642,6 +642,11 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
     }
 #endif
 
+#if SOC_INT_PLIC_SUPPORTED
+    /* Make sure the interrupt is not delegated to user mode (IDF uses machine mode only) */
+    RV_CLEAR_CSR(mideleg, BIT(intr));
+#endif
+
     portEXIT_CRITICAL(&spinlock);
 
     //Fill return handle if needed, otherwise free handle.

components/esp_hw_support/port/esp32/esp_cpu_intr.c

@@ -22,20 +22,146 @@ typedef struct {
 } intr_desc_t;
 
 
+/**
+ * @brief Reserve interrupt 5 or 25 for Bluetooth BR/EDR and BLE controller.
+ */
+#if CONFIG_BTDM_CTRL_HLI
+    #define STATE_INTERRUPT_5    0
+    #define STATE_INTERRUPT_25   ESP_CPU_INTR_DESC_FLAG_RESVD
+#else // !CONFIG_BTDM_CTRL_HLI
+    #define STATE_INTERRUPT_5    ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define STATE_INTERRUPT_25   0
+#endif // CONFIG_BTDM_CTRL_HLI
+
+
+/**
+ * @brief Interrupt 1 is used by UART HCI, regardless of High-Level Interrupt (HLI) configuration
+ */
+#if CONFIG_BTDM_CTRL_HCI_MODE_UART_H4
+    #define STATE_INTERRUPT_1   ESP_CPU_INTR_DESC_FLAG_RESVD
+    /* Interrupt 7 being a software interrupt, it is marked as "special" if not used */
+    #define STATE_INTERRUPT_7   ESP_CPU_INTR_DESC_FLAG_SPECIAL
+#else // !BTDM_CTRL_HCI_MODE_UART_H4
+    #define STATE_INTERRUPT_1   0
+    #define STATE_INTERRUPT_7   ESP_CPU_INTR_DESC_FLAG_RESVD
+#endif // BTDM_CTRL_HCI_MODE_UART_H4
+
+
+/**
+ * @brief Reserve the interrupts on the core where Bluetooth will run.
+ * The macro CONFIG_BTDM_CTRL_PINNED_TO_CORE is only defined if Bluetooth controller is enabled.
+ * It is set to the core where it will run.
+ */
+#ifdef CONFIG_BTDM_CTRL_PINNED_TO_CORE
+    #if CONFIG_BTDM_CTRL_PINNED_TO_CORE == 0
+        /* Interrupt 1 is used by Bluetooth UART HCI, check code above */
+        #define CORE_0_INTERRUPT_1  STATE_INTERRUPT_1
+        #define CORE_1_INTERRUPT_1  0
+        /* Interrupt 5 may be used by Bluetooth BR/EDR and BLE controller */
+        #define CORE_0_INTERRUPT_5  STATE_INTERRUPT_5
+        #define CORE_1_INTERRUPT_5  0
+        /* Interrupt 7 is used by Bluetooth VHCI software interrupt */
+        #define CORE_0_INTERRUPT_7  STATE_INTERRUPT_7
+        #define CORE_1_INTERRUPT_7  ESP_CPU_INTR_DESC_FLAG_SPECIAL
+        /* Interrupt 8 is used by Bluetooth BB */
+        #define CORE_0_INTERRUPT_8  ESP_CPU_INTR_DESC_FLAG_RESVD
+        #define CORE_1_INTERRUPT_8  0
+        /* Interrupt 25 may be used by Bluetooth BR/EDR and BLE controller */
+        #define CORE_0_INTERRUPT_25 STATE_INTERRUPT_25
+        #define CORE_1_INTERRUPT_25 0
+    #elif CONFIG_BTDM_CTRL_PINNED_TO_CORE == 1
+        /* Interrupt 1 is used by Bluetooth UART HCI, check code above */
+        #define CORE_0_INTERRUPT_1  0
+        #define CORE_1_INTERRUPT_1  STATE_INTERRUPT_1
+        /* Interrupt 5 may be used by Bluetooth BR/EDR and BLE controller */
+        #define CORE_0_INTERRUPT_5  0
+        #define CORE_1_INTERRUPT_5  STATE_INTERRUPT_5
+        /* Interrupt 7 is used by Bluetooth VHCI software interrupt */
+        #define CORE_0_INTERRUPT_7  ESP_CPU_INTR_DESC_FLAG_SPECIAL
+        #define CORE_1_INTERRUPT_7  STATE_INTERRUPT_7
+        /* Interrupt 8 is used by Bluetooth BB */
+        #define CORE_0_INTERRUPT_8  0
+        #define CORE_1_INTERRUPT_8  ESP_CPU_INTR_DESC_FLAG_RESVD
+        /* Interrupt 25 may be used by Bluetooth BR/EDR and BLE controller */
+        #define CORE_0_INTERRUPT_25 0
+        #define CORE_1_INTERRUPT_25 STATE_INTERRUPT_25
+    #endif
+#else // Bluetooth not enabled
+    #define CORE_0_INTERRUPT_1  0
+    #define CORE_1_INTERRUPT_1  0
+    #define CORE_0_INTERRUPT_5  0
+    #define CORE_1_INTERRUPT_5  0
+    #define CORE_0_INTERRUPT_7  ESP_CPU_INTR_DESC_FLAG_SPECIAL
+    #define CORE_1_INTERRUPT_7  ESP_CPU_INTR_DESC_FLAG_SPECIAL
+    #define CORE_0_INTERRUPT_8  0
+    #define CORE_1_INTERRUPT_8  0
+    #define CORE_0_INTERRUPT_25 0
+    #define CORE_1_INTERRUPT_25 0
+#endif
+
+
+/**
+ * @brief The system interrupts (memory access, cache, watchdog, ...) can be allocated on either level 4 or level 5 interrupts.
+ * Check the configuration.
+ */
+#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
+    #define CORE_0_INTERRUPT_24 0
+    #define CORE_1_INTERRUPT_24 0
+    /* If CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled, Bluetooth macros above take care of interrupt 25 */
+    /* Interrupt 26 reserved for T1 Watchdog, cache and memory access errors  */
+    #define CORE_0_INTERRUPT_26 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define CORE_1_INTERRUPT_26 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define CORE_0_INTERRUPT_28 0
+    #define CORE_1_INTERRUPT_28 0
+    /* Interrupt 31 reserved for IPC ISRs */
+    #define CORE_0_INTERRUPT_31 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define CORE_1_INTERRUPT_31 ESP_CPU_INTR_DESC_FLAG_RESVD
+#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
+    /* Interrupt reserved for T1 Watchdog, make sure it is enabled */
+    #if CONFIG_ESP_INT_WDT
+        #define CORE_0_INTERRUPT_24 ESP_CPU_INTR_DESC_FLAG_RESVD
+        #define CORE_1_INTERRUPT_24 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #else // !CONFIG_ESP_INT_WDT
+        #define CORE_0_INTERRUPT_24 0
+        #define CORE_1_INTERRUPT_24 0
+    #endif
+    /* If CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled, Bluetooth HLI is not enabled for sure (guaranteed by Kconfig),
+     * so we can discard the macro previously defined for interrupt 25 */
+    #undef CORE_0_INTERRUPT_25
+    #undef CORE_1_INTERRUPT_25
+    /* Interrupt reserved for memory access and cache errors */
+    #define CORE_0_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define CORE_1_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define CORE_0_INTERRUPT_26 0
+    #define CORE_1_INTERRUPT_26 0
+    /* Interrupt reserved for IPC ISRs */
+    #define CORE_0_INTERRUPT_28 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define CORE_1_INTERRUPT_28 ESP_CPU_INTR_DESC_FLAG_RESVD
+    #define CORE_0_INTERRUPT_31 0
+    #define CORE_1_INTERRUPT_31 0
+#endif // CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
+
+
 const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
+    /* Interrupt 0 reserved for WMAC (Wifi) */
     [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
-    [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
+    /* Interrupt 1 reserved for BT/BLE Host HCI DMA when CONFIG_BTDM_CTRL_HCI_MODE_UART_H4 is enabled */
+    [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { CORE_0_INTERRUPT_1,             CORE_1_INTERRUPT_1              } },
     [2] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { 0,                              0                               } },
     [3] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { 0,                              0                               } },
+    /* Interrupt 4 reserved for WBB */
     [4] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { ESP_CPU_INTR_DESC_FLAG_RESVD,   0                               } },
-    [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
+    /* Interrupt 5 reserved for BT/BLE Controller when Bluetooth HLI is enabled */
+    [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { CORE_0_INTERRUPT_5,             CORE_1_INTERRUPT_5              } },
 #if CONFIG_FREERTOS_CORETIMER_0
     [6] = { 1, ESP_CPU_INTR_TYPE_NA,     { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
 #else
     [6] = { 1, ESP_CPU_INTR_TYPE_NA,     { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL  } },
 #endif
-    [7] = { 1, ESP_CPU_INTR_TYPE_NA,     { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL  } },
-    [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
+    /* Interrupt 7 reserved for Bluetooth VHCI (software interrupt) */
+    [7] = { 1, ESP_CPU_INTR_TYPE_NA,     { CORE_0_INTERRUPT_7,             CORE_1_INTERRUPT_7              } },
+    /* Interrupt 8 reserved for BT/BLE BB(RX/TX) */
+    [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { CORE_0_INTERRUPT_8,             CORE_1_INTERRUPT_8              } },
     [9] = { 1, ESP_CPU_INTR_TYPE_LEVEL,  { 0,                              0                               } },
     [10] = { 1, ESP_CPU_INTR_TYPE_EDGE,  { 0,                              0                               } },
     [11] = { 3, ESP_CPU_INTR_TYPE_NA,    { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL  } },
@@ -53,16 +179,22 @@ const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
     [19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0,                              0                               } },
     [20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0,                              0                               } },
     [21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0,                              0                               } },
-    [22] = { 3, ESP_CPU_INTR_TYPE_EDGE,  { ESP_CPU_INTR_DESC_FLAG_RESVD,   0                               } },
+    [22] = { 3, ESP_CPU_INTR_TYPE_EDGE,  { 0,                              0                               } },
     [23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0,                              0                               } },
-    [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD,   0                               } },
-    [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
-    [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0,                              ESP_CPU_INTR_DESC_FLAG_RESVD    } },
-    [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
-    [28] = { 4, ESP_CPU_INTR_TYPE_EDGE,  { 0,                              0                               } },
+    /* Interrupt 24 reserved for T1 WDT when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled */
+    [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_24,            CORE_1_INTERRUPT_24             } },
+    /* Interrupt 25 reserved for Memory access and cache errors when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled
+     * Reserved for BT/BLE Controller when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */
+    [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_25,            CORE_1_INTERRUPT_25             } },
+    /* Interrupt 26 reserved for T1 WDT, Memory access and cache errors when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */
+    [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_26,            CORE_1_INTERRUPT_26             } },
+    [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0,                              0                               } },
+    /* Interrupt 28 reserved for IPC when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled */
+    [28] = { 4, ESP_CPU_INTR_TYPE_EDGE,  { CORE_0_INTERRUPT_28,            CORE_1_INTERRUPT_28             } },
     [29] = { 3, ESP_CPU_INTR_TYPE_NA,    { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL  } },
-    [30] = { 4, ESP_CPU_INTR_TYPE_EDGE,  { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
-    [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD,   ESP_CPU_INTR_DESC_FLAG_RESVD    } },
+    [30] = { 4, ESP_CPU_INTR_TYPE_EDGE,  { 0,                              0                               } },
+    /* Interrupt 31 reserved for IPC when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */
+    [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_31,            CORE_1_INTERRUPT_31             } },
 };
 
 

components/esp_hw_support/port/esp32c2/esp_cpu_intr.c

@@ -11,11 +11,10 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
 {
     /* On the ESP32-C2, interrupt:
      * - 1 is for Wi-Fi
-     * - 5 and 8 for Bluetooth
-     * - 6 for "permanently disabled interrupt"
+     * - 6 for "permanently disabled interrupt", named INT_MUX_DISABLED_INTNO in the interrupt allocator
      */
     // [TODO: IDF-2465]
-    const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8);
+    const uint32_t rsvd_mask = BIT(1) | BIT(6);
 
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

components/esp_hw_support/port/esp32c3/esp_cpu_intr.c

@@ -12,7 +12,7 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
     /* On the ESP32-C3, interrupt:
      * - 1 is for Wi-Fi
      * - 5 and 8 for Bluetooth
-     * - 6 for "permanently disabled interrupt"
+     * - 6 for "permanently disabled interrupt", named INT_MUX_DISABLED_INTNO in the interrupt allocator
      */
     // [TODO: IDF-2465]
     const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8);

components/esp_hw_support/port/esp32c5/esp_cpu_intr.c

@@ -12,9 +12,11 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
     /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
      * interrupts, all the other lines starting from 16 and above can be used by external peripheral.
      *
-     * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
-    /* TODO: IDF-8655, we may need to reserve more interrupts once we have Wifi and BT */
+     * Reserve interrupt line 1 for the Wifi controller.
+     * Reserve interrupt line 6 since it is used for disabling interrupts in the interrupt allocator (INT_MUX_DISABLED_INTNO)
+     */
+    const uint32_t rsvd_mask = BIT(1) | BIT(6);
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
-    intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
+    intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
 }

components/esp_hw_support/port/esp32c6/esp_cpu_intr.c

@@ -11,14 +11,12 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
 {
     /* On the ESP32-C6, interrupt:
      * - 1 is for Wi-Fi
-     * - 5 and 8 for Bluetooth
      * - 6 for "permanently disabled interrupt"
      *
-     * Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU.
+     * Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
      */
     // [TODO: IDF-2465]
-    const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) |
-                               BIT(5) | BIT(6) | BIT(7) | BIT(8);
+    const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
 
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

components/esp_hw_support/port/esp32h2/esp_cpu_intr.c

@@ -11,14 +11,12 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
 {
     /* On the ESP32-H2, interrupt:
      * - 1 is for Wi-Fi
-     * - 5 and 8 for Bluetooth
      * - 6 for "permanently disabled interrupt"
      *
-     * Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU.
+     * Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
      */
     // [TODO: IDF-2465]
-    const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) |
-                               BIT(5) | BIT(6) | BIT(7) | BIT(8);
+    const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
 
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

components/esp_hw_support/port/esp32p4/esp_cpu_intr.c

@@ -12,8 +12,11 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
     /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
      * interrupts, all the other lines starting from 16 and above can be used by external peripheral.
      *
-     * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
+     * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts in the
+     * interrupt allocator (INT_MUX_DISABLED_INTNO) */
+    const uint32_t rsvd_mask = BIT(6);
+
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
-    intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
+    intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
 }