Merge branch 'bugfix/fix_i2s_ll_cpp_compilation_failure_v5.1' into 'r…

…elease/v5.1'

i2s: fixed i2s_ll compiling failure under C++ environment (v5.1)

See merge request espressif/esp-idf!24401

components/driver/dac/esp32/dac_dma.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,7 @@
 #include "freertos/FreeRTOS.h"
 #include "sdkconfig.h"
 #include "hal/adc_ll.h"
-#include "hal/i2s_ll.h"
+#include "hal/i2s_hal.h"
 #include "hal/i2s_types.h"
 #include "soc/i2s_periph.h"
 #include "../dac_priv_dma.h"
@@ -97,7 +97,9 @@ static esp_err_t s_dac_dma_periph_set_clock(uint32_t freq_hz, bool is_apll)
     ESP_LOGD(TAG, "[sclk] %"PRIu32" [mclk] %"PRIu32" [mclk_div] %"PRIu32" [bclk] %"PRIu32" [bclk_div] %"PRIu32, sclk, mclk, mclk_div, bclk, bclk_div);
 
     i2s_ll_tx_clk_set_src(s_ddp->periph_dev, is_apll ? I2S_CLK_SRC_APLL : I2S_CLK_SRC_DEFAULT);
-    i2s_ll_tx_set_mclk(s_ddp->periph_dev, sclk, mclk, mclk_div);
+    i2s_ll_mclk_div_t mclk_div_coeff = {};
+    i2s_hal_calc_mclk_precise_division(sclk, mclk, &mclk_div_coeff);
+    i2s_ll_tx_set_mclk(s_ddp->periph_dev, &mclk_div_coeff);
     i2s_ll_tx_set_bck_div_num(s_ddp->periph_dev, bclk_div);
 
     return ESP_OK;

components/driver/i2s/i2s_pdm.c

@@ -70,7 +70,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
 #if SOC_I2S_HW_VERSION_2
     /* Work around for PDM TX clock, overwrite the raw division directly to reduce the noise
      * This set of coefficients is a special division to reduce the background noise in PDM TX mode */
-    i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, 1, 1, 0, 0);
+    i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, clk_info.mclk_div, 1, 1, 0, 0);
 #endif
     portEXIT_CRITICAL(&g_i2s.spinlock);
 

components/hal/adc_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,7 +13,7 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 //ADC utilises I2S0 DMA on ESP32
-#include "hal/i2s_ll.h"
+#include "hal/i2s_hal.h"
 #include "hal/i2s_types.h"
 #include "soc/i2s_struct.h"
 #endif
@@ -179,8 +179,9 @@ static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuo
     uint32_t bclk_div = 16;
     uint32_t bclk = sample_freq_hz * 2;
     uint32_t mclk = bclk * bclk_div;
-    uint32_t mclk_div = I2S_BASE_CLK / mclk;
-    i2s_ll_rx_set_mclk(hal->dev, I2S_BASE_CLK, mclk, mclk_div);
+    i2s_ll_mclk_div_t mclk_div = {};
+    i2s_hal_calc_mclk_precise_division(I2S_BASE_CLK, mclk, &mclk_div);
+    i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
     i2s_ll_rx_set_bck_div_num(hal->dev, bclk_div);
 #endif
 }

components/hal/esp32/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -48,11 +48,14 @@ extern "C" {
 #define I2S_LL_PLL_F160M_CLK_FREQ   (160 * 1000000) // PLL_F160M_CLK: 160MHz
 #define I2S_LL_DEFAULT_PLL_CLK_FREQ     I2S_LL_PLL_F160M_CLK_FREQ    // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
 
-/* I2S clock configuration structure */
+/**
+ * @brief I2S clock configuration structure
+ * @note Fmclk = Fsclk /(integ+numer/denom)
+ */
 typedef struct {
-    uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
-    uint16_t a;
-    uint16_t b;        // The decimal part of module clock divider, the decimal is: b/a
+    uint16_t integ;     // Integer part of I2S module clock divider
+    uint16_t denom;     // Denominator part of I2S module clock divider
+    uint16_t numer;     // Numerator part of I2S module clock divider
 } i2s_ll_mclk_div_t;
 
 /**
@@ -286,68 +289,37 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 }
 
 /**
- * @brief Configure I2S TX module clock divider
+ * @brief Configure I2S module clock divider
  * @note mclk on ESP32 is shared by both TX and RX channel
+ *       mclk = sclk / (mclk_div + b/a)
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
  * @param mclk_div integer part of the division from sclk to mclk
+ * @param a Denominator of decimal part
+ * @param b Numerator of decimal part
  */
-static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uint32_t a, uint32_t b)
 {
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, mclk_div);
-    hw->clkm_conf.clkm_div_b = numerator;
-    hw->clkm_conf.clkm_div_a = denominator;
+    hw->clkm_conf.clkm_div_b = b;
+    hw->clkm_conf.clkm_div_a = a;
 }
 
 /**
- * @brief Configure I2S module clock divider
+ * @brief Configure I2S TX module clock divider
  * @note mclk on ESP32 is shared by both TX and RX channel
- *       mclk = sclk / (mclk_div + b/a)
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param mclk_div integer part of the division from sclk to mclk
- * @param a Denominator of decimal part
- * @param b Numerator of decimal part
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uint32_t a, uint32_t b)
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, mclk_div);
-    hw->clkm_conf.clkm_div_b = b;
-    hw->clkm_conf.clkm_div_a = a;
+    /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
+     * Set to particular coefficients first then update to the target coefficients,
+     * otherwise the clock division might be inaccurate.
+     * the general idea is to set a value that unlike to calculate from the regular decimal */
+    i2s_ll_set_raw_mclk_div(hw, 7, 47, 3);
+    i2s_ll_set_raw_mclk_div(hw, mclk_div->integ, mclk_div->denom, mclk_div->numer);
 }
 
 /**
@@ -366,13 +338,12 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    i2s_ll_tx_set_mclk(hw, sclk, mclk, mclk_div);
+    // TX and RX channel on ESP32 shares a same mclk
+    i2s_ll_tx_set_mclk(hw, mclk_div);
 }
 
 /**
@@ -384,11 +355,13 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
  */
 static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
 {
+    uint32_t int_ena_mask = hw->int_ena.val;
     if (en) {
-        hw->int_ena.val |= mask;
+        int_ena_mask |= mask;
     } else {
-        hw->int_ena.val &= ~mask;
+        int_ena_mask &= ~mask;
     }
+    hw->int_ena.val = int_ena_mask;
 }
 
 /**