ulp-riscv: enable ULP-RISCV ADC example for esp32s2

ADC can now be used from the ULP-RISCV on S2 after the RTC power parameters were fixed in a624d8d Closes #11052 Closes #11040
espressif · Apr 24, 2023 · 0747101 · 0747101
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commit 0747101
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diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml
@@ -154,7 +154,7 @@ examples/system/ulp_fsm/ulp_adc:
 
 examples/system/ulp_riscv/adc:
   enable:
-    - if: IDF_TARGET in ["esp32s3"]
+    - if: IDF_TARGET in ["esp32s2", "esp32s3"]
       temporary: true
       reason: the other targets are not tested yet
 

diff --git a/examples/system/ulp_riscv/adc/README.md b/examples/system/ulp_riscv/adc/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-S3 |
-| ----------------- | -------- |
+| Supported Targets | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- |
 
 # ULP-RISC-V ADC Example