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Merge branch 'feature/esp32p4_update_systimer' into 'master'
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feat(esp_timer): Support systimer for ESP32P4

Closes IDF-7486 and IDF-7487

See merge request espressif/esp-idf!25688
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KonstantinKondrashov committed Sep 13, 2023
2 parents ea60282 + cbdb799 commit 054d494
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Showing 22 changed files with 416 additions and 319 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,7 @@ gptimer_handle_t s_sv_gptimer;
#endif

#elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_INTR_SOURCE)
#endif // CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER

// SystemView is single core specific: it implies that SEGGER_SYSVIEW_LOCK()
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15 changes: 14 additions & 1 deletion components/esp_hw_support/hw_random.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -34,6 +34,18 @@
#define APB_CYCLE_WAIT_NUM (16)
#endif

#if CONFIG_IDF_TARGET_ESP32P4
#include "esp_log.h"
static const char *TAG = "hw_random";

uint32_t IRAM_ATTR esp_random(void)
{
// TODO: IDF-6522
ESP_EARLY_LOGW(TAG, "esp_random() has not been implemented yet");
return 0xDEADBEEF;
}
#else // !CONFIG_IDF_TARGET_ESP32P4

uint32_t IRAM_ATTR esp_random(void)
{
/* The PRNG which implements WDEV_RANDOM register gets 2 bits
Expand Down Expand Up @@ -77,6 +89,7 @@ uint32_t IRAM_ATTR esp_random(void)
last_ccount = ccount;
return result ^ REG_READ(WDEV_RND_REG);
}
#endif //!CONFIG_IDF_TARGET_ESP32P4

void esp_fill_random(void *buf, size_t len)
{
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5 changes: 4 additions & 1 deletion components/esp_hw_support/port/esp32p4/systimer.c
Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,12 @@
#include "esp_private/systimer.h"

/**
* //TODO: IDF-7487
* @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
* So the resolution of the systimer is 40MHz/2.5 = 16MHz.
*
* FPGA esp32p4 image:
* - v10.0.0 (old) has 20MHz
* - v12.0.0 has 16MHz
*/

uint64_t systimer_ticks_to_us(uint64_t ticks)
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4 changes: 2 additions & 2 deletions components/esp_rom/patches/esp_rom_systimer.c
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
}
#endif // CONFIG_IDF_TARGET_ESP32C2

#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
void systimer_hal_init(systimer_hal_context_t *hal)
{
hal->dev = &SYSTIMER;
Expand All @@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal)
systimer_ll_enable_clock(hal->dev, false);
hal->dev = NULL;
}
#endif // CONFIG_IDF_TARGET_ESP32C6
#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4

#endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
7 changes: 0 additions & 7 deletions components/esp_timer/src/esp_timer_impl_systimer.c
Original file line number Diff line number Diff line change
Expand Up @@ -192,16 +192,9 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
#endif
| ESP_INTR_FLAG_IRAM;

#if !CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7486
esp_err_t err = esp_intr_alloc(ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, isr_flags,
&timer_alarm_isr, NULL,
&s_timer_interrupt_handle[(ISR_HANDLERS == 1) ? 0 : xPortGetCoreID()]);
#else
esp_err_t err = esp_intr_alloc(ETS_SYSTIMER_TARGET2_INTR_SOURCE, isr_flags,
&timer_alarm_isr, NULL,
&s_timer_interrupt_handle[(ISR_HANDLERS == 1) ? 0 : xPortGetCoreID()]);
#endif
if (err != ESP_OK) {
ESP_EARLY_LOGE(TAG, "esp_intr_alloc failed (0x%x)", err);
return err;
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@
#include "esp_rom_sys.h"
#include "esp_sleep.h"

#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6) // TODO IDF-6770
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7528

static void timer_cb1(void *arg)
{
Expand Down Expand Up @@ -53,4 +53,4 @@ TEST_CASE("Test the periodic timer does not handle lost events during light slee
TEST_ESP_OK(esp_timer_delete(periodic_timer));
}

#endif //#!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
#endif //#!TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4)
14 changes: 1 addition & 13 deletions components/esp_timer/test_apps/main/test_ets_timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -15,19 +15,7 @@
#include "spi_flash_mmap.h"
#include "esp_rom_sys.h"
#include "esp_private/spi_flash_os.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // for ETSTimer type
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C6
#include "esp32c6/rom/ets_sys.h"
#endif
#include "rom/ets_sys.h"

static void test_correct_delay_timer_func(void* arg)
{
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11 changes: 1 addition & 10 deletions components/freertos/port_systick.c
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@
#define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF)
#endif
#else /* CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER */
#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_INTR_SOURCE)
#endif /* CONFIG_FREERTOS_SYSTICK_USES_CCOUNT */

BaseType_t xPortSysTickHandler(void);
Expand Down Expand Up @@ -69,16 +69,7 @@ void vSystimerSetup(void)
static systimer_hal_context_t systimer_hal;
/* set system timer interrupt vector */

/**
* TODO: IDF-7487
* ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE is renamed to ETS_SYSTIMER_TARGET0_INTR_SOURCE.
* It's said that this interrupt is never an edge type, for previous all chips. You may need to check this and unify the name.
*/
#if !CONFIG_IDF_TARGET_ESP32P4
ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
#else
ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
#endif

if (cpuid == 0) {
periph_module_enable(PERIPH_SYSTIMER_MODULE);
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12 changes: 9 additions & 3 deletions components/hal/esp32p4/include/hal/systimer_ll.h
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
#include "soc/systimer_struct.h"
#include "soc/clk_tree_defs.h"
#include "hal/assert.h"
#include "soc/hp_sys_clkrst_struct.h"

#ifdef __cplusplus
extern "C" {
Expand All @@ -18,8 +19,6 @@ extern "C" {
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no gcc optimization is applied.

//TODO: IDF-7486

/******************* Clock *************************/

__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
Expand All @@ -30,17 +29,24 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systi
// Set clock source: XTAL(default) or RC_FAST
static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src)
{
HP_SYS_CLKRST.peri_clk_ctrl21.reg_systimer_clk_src_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0;
}

/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define systimer_ll_set_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; systimer_ll_set_clock_source(__VA_ARGS__)


static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void)
{
return SYSTIMER_CLK_SRC_XTAL;
return (HP_SYS_CLKRST.peri_clk_ctrl21.reg_systimer_clk_src_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
}

/********************** ETM *****************************/

__attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en)
{
dev->conf.etm_en = en;
}

/******************* Counter *************************/
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3 changes: 3 additions & 0 deletions components/hal/include/hal/systimer_hal.h
Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,9 @@ void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_sour

/**
* @brief Set Systimer clock source
*
* Use this function as - PERIPH_RCC_ATOMIC(){ systimer_hal_set_clock_source(hal, clk_src); }
* due to Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
*/
void systimer_hal_set_clock_source(systimer_hal_context_t *hal, systimer_clock_source_t clk_src);

Expand Down
3 changes: 2 additions & 1 deletion components/hal/systimer_hal.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand All @@ -12,6 +12,7 @@
#include "hal/systimer_types.h"
#include "hal/assert.h"


void systimer_hal_init(systimer_hal_context_t *hal)
{
hal->dev = &SYSTIMER;
Expand Down
11 changes: 7 additions & 4 deletions components/soc/esp32c2/include/soc/interrupts.h
Original file line number Diff line number Diff line change
Expand Up @@ -41,10 +41,13 @@ typedef enum {
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE = 29, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/
ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
Expand Down
11 changes: 7 additions & 4 deletions components/soc/esp32c3/include/soc/interrupts.h
Original file line number Diff line number Diff line change
Expand Up @@ -52,10 +52,13 @@ typedef enum {
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE = 40, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/
ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
Expand Down
11 changes: 7 additions & 4 deletions components/soc/esp32c6/include/soc/interrupts.h
Original file line number Diff line number Diff line change
Expand Up @@ -72,10 +72,13 @@ typedef enum {
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
ETS_APB_ADC_INTR_SOURCE = 60, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_INTR_SOURCE,
Expand Down
11 changes: 7 additions & 4 deletions components/soc/esp32h2/include/soc/interrupts.h
Original file line number Diff line number Diff line change
Expand Up @@ -60,10 +60,13 @@ typedef enum {
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
ETS_APB_ADC_INTR_SOURCE = 48, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE,
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
Expand Down
1 change: 0 additions & 1 deletion components/soc/esp32p4/include/soc/clk_tree_defs.h
Original file line number Diff line number Diff line change
Expand Up @@ -155,7 +155,6 @@ typedef enum {

//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////

//TODO: IDF-7486
/**
* @brief Type of SYSTIMER clock source
*/
Expand Down
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