Merge branch 'bugfix/ota_fail_on_octal_flash' into 'master'

fix(ota): Fixed OTA fail on octal flash with 32MB memory

See merge request espressif/esp-idf!26436

Kconfig

@@ -589,5 +589,5 @@ mainmenu "Espressif IoT Development Framework Configuration"
 
             - CONFIG_ESPTOOLPY_FLASHFREQ_120M
             - CONFIG_SPIRAM_SPEED_120M
-            - CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE
+            - CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE
             - CONFIG_FREERTOS_USE_KERNEL_10_5_1

components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h

@@ -109,7 +109,7 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup
   */
 esp_err_t __attribute__((weak)) bootloader_flash_unlock(void);
 
-#if CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE
+#if CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE || CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
 /**
  * @brief Enable 32bits address flash(larger than 16MB) can map to cache.
  *

components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h

@@ -56,6 +56,8 @@ extern "C" {
 #define CMD_FASTRD_QUAD_4B  0x6C
 #define CMD_FASTRD_DIO_4B   0xBC
 #define CMD_FASTRD_DUAL_4B  0x3C
+#define CMD_FASTRD_4B       0x0C
+#define CMD_SLOWRD_4B       0x13
 
 
 /* Provide a Flash API for bootloader_support code,

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -426,7 +426,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
     return spi_to_esp_err(rc);
 }
 
-#if CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE
+#if CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE || CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
 void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode)
 {
     esp_rom_opiflash_spi0rd_t cache_rd = {};
@@ -455,6 +455,18 @@ void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t fla
         cache_rd.cmd = CMD_FASTRD_QIO_4B;
         cache_rd.cmd_bit_len = 8;
         break;
+    case ESP_ROM_SPIFLASH_FASTRD_MODE:
+        cache_rd.addr_bit_len = 32;
+        cache_rd.dummy_bit_len = 8;
+        cache_rd.cmd = CMD_FASTRD_4B;
+        cache_rd.cmd_bit_len = 8;
+        break;
+     case ESP_ROM_SPIFLASH_SLOWRD_MODE:
+        cache_rd.addr_bit_len = 32;
+        cache_rd.dummy_bit_len = 0;
+        cache_rd.cmd = CMD_SLOWRD_4B;
+        cache_rd.cmd_bit_len = 8;
+        break;
     default:
         assert(false);
         break;

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c

@@ -288,7 +288,7 @@ esp_err_t bootloader_init_spi_flash(void)
         bootloader_enable_qio_mode();
     }
 #endif
-#if CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE
+#if CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE || CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
     bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
 #endif
     print_flash_info(&bootloader_image_hdr);

components/esp_rom/patches/esp_rom_spiflash.c

@@ -11,6 +11,9 @@
 #include "esp32/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/spi_flash.h"
+#include "esp32s3/rom/opi_flash.h"
 #endif
 
 #define SPI_IDX   1
@@ -697,6 +700,31 @@ esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
     return ESP_ROM_SPIFLASH_RESULT_OK;
 }
 
+#elif CONFIG_IDF_TARGET_ESP32S3
+extern void esp_rom_spi_set_address_bit_len(int spi, int addr_bits);
+void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache)
+{
+    esp_rom_spi_set_op_mode(0, mode);
+    REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MOSI);
+    REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MISO | SPI_MEM_USR_ADDR);
+
+    if (cache) {
+        esp_rom_spi_set_address_bit_len(0, cache->addr_bit_len);
+        // Patch for ROM function `esp_rom_opiflash_cache_mode_config`, because when dummy is 0,
+        // `SPI_MEM_USR_DUMMY` should be 0. `esp_rom_opiflash_cache_mode_config` doesn't handle this
+        // properly.
+        if (cache->dummy_bit_len == 0) {
+            REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
+        } else {
+            REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
+            REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, cache->dummy_bit_len - 1 + rom_spiflash_legacy_data->dummy_len_plus[0]);
+        }
+        REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, cache->cmd);
+        REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_BITLEN, cache->cmd_bit_len - 1);
+        REG_SET_FIELD(SPI_MEM_DDR_REG(0), SPI_MEM_SPI_FMEM_VAR_DUMMY, cache->var_dummy_en);
+    }
+}
+
 #endif // IDF_TARGET
 
 #endif // CONFIG_SPI_FLASH_ROM_DRIVER_PATCH

components/spi_flash/Kconfig

@@ -329,7 +329,7 @@ menu "SPI Flash driver"
         help
             This is a helper config for 32bits address flash. Invisible for users.
 
-    config SPI_FLASH_32BIT_ADDR_ENABLE
+    config SPI_FLASH_QUAD_32BIT_ADDR_ENABLE
         bool "Enable 32-bit-address (over 16MB) SPI Flash access"
         depends on SPI_FLASH_32BIT_ADDRESS && !ESPTOOLPY_OCT_FLASH && IDF_TARGET_ESP32S3 && IDF_EXPERIMENTAL_FEATURES
         default n
@@ -339,4 +339,9 @@ menu "SPI Flash driver"
             2. This option is experimental, which means it can't use on all flash chips stable, for more
             information, please contact Espressif Business support.
 
+    config SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
+        bool
+        default y if ESPTOOLPY_OCT_FLASH && SPI_FLASH_32BIT_ADDRESS
+        default n
+
 endmenu

components/spi_flash/sdkconfig.rename

@@ -5,3 +5,4 @@ CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS              CONFIG_SPI_FLASH_DANGERO
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS       CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS        CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED      CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED
+CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE                      CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE