Patch the GDMA peripheral for ESP32-C2/C3/S3 to make it more consistent

esp32c2/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "esp32c2"
-version = "0.3.0"
+version = "0.4.0"
 authors = ["Jesse Braham <[email protected]>"]
 edition = "2021"
 description = "Peripheral access crate for the ESP32-C2"

esp32c2/src/dma/in_conf0_ch0.rs

@@ -34,82 +34,79 @@ impl From<crate::W<IN_CONF0_CH0_SPEC>> for W {
         W(writer)
     }
 }
-#[doc = "Field `IN_RST_CH0` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
-pub type IN_RST_CH0_R = crate::BitReader<bool>;
-#[doc = "Field `IN_RST_CH0` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
-pub type IN_RST_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
-#[doc = "Field `IN_LOOP_TEST_CH0` reader - reserved"]
-pub type IN_LOOP_TEST_CH0_R = crate::BitReader<bool>;
-#[doc = "Field `IN_LOOP_TEST_CH0` writer - reserved"]
-pub type IN_LOOP_TEST_CH0_W<'a, const O: u8> =
-    crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
-#[doc = "Field `INDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
-pub type INDSCR_BURST_EN_CH0_R = crate::BitReader<bool>;
-#[doc = "Field `INDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
-pub type INDSCR_BURST_EN_CH0_W<'a, const O: u8> =
-    crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
-#[doc = "Field `IN_DATA_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
-pub type IN_DATA_BURST_EN_CH0_R = crate::BitReader<bool>;
-#[doc = "Field `IN_DATA_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
-pub type IN_DATA_BURST_EN_CH0_W<'a, const O: u8> =
-    crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
-#[doc = "Field `MEM_TRANS_EN_CH0` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
-pub type MEM_TRANS_EN_CH0_R = crate::BitReader<bool>;
-#[doc = "Field `MEM_TRANS_EN_CH0` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
-pub type MEM_TRANS_EN_CH0_W<'a, const O: u8> =
+#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
+pub type IN_RST_R = crate::BitReader<bool>;
+#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
+pub type IN_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
+#[doc = "Field `IN_LOOP_TEST` reader - reserved"]
+pub type IN_LOOP_TEST_R = crate::BitReader<bool>;
+#[doc = "Field `IN_LOOP_TEST` writer - reserved"]
+pub type IN_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
+#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type INDSCR_BURST_EN_R = crate::BitReader<bool>;
+#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type INDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
+#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+pub type IN_DATA_BURST_EN_R = crate::BitReader<bool>;
+#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+pub type IN_DATA_BURST_EN_W<'a, const O: u8> =
     crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
+#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
+pub type MEM_TRANS_EN_R = crate::BitReader<bool>;
+#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
+pub type MEM_TRANS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>;
 impl R {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
-    pub fn in_rst_ch0(&self) -> IN_RST_CH0_R {
-        IN_RST_CH0_R::new((self.bits & 1) != 0)
+    pub fn in_rst(&self) -> IN_RST_R {
+        IN_RST_R::new((self.bits & 1) != 0)
     }
     #[doc = "Bit 1 - reserved"]
     #[inline(always)]
-    pub fn in_loop_test_ch0(&self) -> IN_LOOP_TEST_CH0_R {
-        IN_LOOP_TEST_CH0_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn in_loop_test(&self) -> IN_LOOP_TEST_R {
+        IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
     #[inline(always)]
-    pub fn indscr_burst_en_ch0(&self) -> INDSCR_BURST_EN_CH0_R {
-        INDSCR_BURST_EN_CH0_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R {
+        INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
     #[inline(always)]
-    pub fn in_data_burst_en_ch0(&self) -> IN_DATA_BURST_EN_CH0_R {
-        IN_DATA_BURST_EN_CH0_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R {
+        IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0)
     }
     #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
     #[inline(always)]
-    pub fn mem_trans_en_ch0(&self) -> MEM_TRANS_EN_CH0_R {
-        MEM_TRANS_EN_CH0_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R {
+        MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0)
     }
 }
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
-    pub fn in_rst_ch0(&mut self) -> IN_RST_CH0_W<0> {
-        IN_RST_CH0_W::new(self)
+    pub fn in_rst(&mut self) -> IN_RST_W<0> {
+        IN_RST_W::new(self)
     }
     #[doc = "Bit 1 - reserved"]
     #[inline(always)]
-    pub fn in_loop_test_ch0(&mut self) -> IN_LOOP_TEST_CH0_W<1> {
-        IN_LOOP_TEST_CH0_W::new(self)
+    pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<1> {
+        IN_LOOP_TEST_W::new(self)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
     #[inline(always)]
-    pub fn indscr_burst_en_ch0(&mut self) -> INDSCR_BURST_EN_CH0_W<2> {
-        INDSCR_BURST_EN_CH0_W::new(self)
+    pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<2> {
+        INDSCR_BURST_EN_W::new(self)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
     #[inline(always)]
-    pub fn in_data_burst_en_ch0(&mut self) -> IN_DATA_BURST_EN_CH0_W<3> {
-        IN_DATA_BURST_EN_CH0_W::new(self)
+    pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<3> {
+        IN_DATA_BURST_EN_W::new(self)
     }
     #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
     #[inline(always)]
-    pub fn mem_trans_en_ch0(&mut self) -> MEM_TRANS_EN_CH0_W<4> {
-        MEM_TRANS_EN_CH0_W::new(self)
+    pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<4> {
+        MEM_TRANS_EN_W::new(self)
     }
     #[doc = "Writes raw bits to the register."]
     #[inline(always)]

esp32c2/src/dma/in_conf1_ch0.rs

@@ -34,23 +34,22 @@ impl From<crate::W<IN_CONF1_CH0_SPEC>> for W {
         W(writer)
     }
 }
-#[doc = "Field `IN_CHECK_OWNER_CH0` reader - Set this bit to enable checking the owner attribute of the link descriptor."]
-pub type IN_CHECK_OWNER_CH0_R = crate::BitReader<bool>;
-#[doc = "Field `IN_CHECK_OWNER_CH0` writer - Set this bit to enable checking the owner attribute of the link descriptor."]
-pub type IN_CHECK_OWNER_CH0_W<'a, const O: u8> =
-    crate::BitWriter<'a, u32, IN_CONF1_CH0_SPEC, bool, O>;
+#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type IN_CHECK_OWNER_R = crate::BitReader<bool>;
+#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type IN_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF1_CH0_SPEC, bool, O>;
 impl R {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
-    pub fn in_check_owner_ch0(&self) -> IN_CHECK_OWNER_CH0_R {
-        IN_CHECK_OWNER_CH0_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R {
+        IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0)
     }
 }
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
-    pub fn in_check_owner_ch0(&mut self) -> IN_CHECK_OWNER_CH0_W<12> {
-        IN_CHECK_OWNER_CH0_W::new(self)
+    pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<12> {
+        IN_CHECK_OWNER_W::new(self)
     }
     #[doc = "Writes raw bits to the register."]
     #[inline(always)]

esp32c2/src/dma/in_dscr_bf0_ch0.rs

@@ -13,13 +13,13 @@ impl From<crate::R<IN_DSCR_BF0_CH0_SPEC>> for R {
         R(reader)
     }
 }
-#[doc = "Field `INLINK_DSCR_BF0_CH0` reader - The address of the last inlink descriptor x-1."]
-pub type INLINK_DSCR_BF0_CH0_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."]
+pub type INLINK_DSCR_BF0_R = crate::FieldReader<u32, u32>;
 impl R {
     #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."]
     #[inline(always)]
-    pub fn inlink_dscr_bf0_ch0(&self) -> INLINK_DSCR_BF0_CH0_R {
-        INLINK_DSCR_BF0_CH0_R::new(self.bits)
+    pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R {
+        INLINK_DSCR_BF0_R::new(self.bits)
     }
 }
 #[doc = "DMA_IN_DSCR_BF0_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf0_ch0](index.html) module"]

esp32c2/src/dma/in_dscr_bf1_ch0.rs

@@ -13,13 +13,13 @@ impl From<crate::R<IN_DSCR_BF1_CH0_SPEC>> for R {
         R(reader)
     }
 }
-#[doc = "Field `INLINK_DSCR_BF1_CH0` reader - The address of the second-to-last inlink descriptor x-2."]
-pub type INLINK_DSCR_BF1_CH0_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."]
+pub type INLINK_DSCR_BF1_R = crate::FieldReader<u32, u32>;
 impl R {
     #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."]
     #[inline(always)]
-    pub fn inlink_dscr_bf1_ch0(&self) -> INLINK_DSCR_BF1_CH0_R {
-        INLINK_DSCR_BF1_CH0_R::new(self.bits)
+    pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R {
+        INLINK_DSCR_BF1_R::new(self.bits)
     }
 }
 #[doc = "DMA_IN_DSCR_BF1_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf1_ch0](index.html) module"]

esp32c2/src/dma/in_dscr_ch0.rs

@@ -13,13 +13,13 @@ impl From<crate::R<IN_DSCR_CH0_SPEC>> for R {
         R(reader)
     }
 }
-#[doc = "Field `INLINK_DSCR_CH0` reader - The address of the current inlink descriptor x."]
-pub type INLINK_DSCR_CH0_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."]
+pub type INLINK_DSCR_R = crate::FieldReader<u32, u32>;
 impl R {
     #[doc = "Bits 0:31 - The address of the current inlink descriptor x."]
     #[inline(always)]
-    pub fn inlink_dscr_ch0(&self) -> INLINK_DSCR_CH0_R {
-        INLINK_DSCR_CH0_R::new(self.bits)
+    pub fn inlink_dscr(&self) -> INLINK_DSCR_R {
+        INLINK_DSCR_R::new(self.bits)
     }
 }
 #[doc = "DMA_IN_DSCR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_ch0](index.html) module"]

esp32c2/src/dma/in_err_eof_des_addr_ch0.rs

@@ -13,13 +13,13 @@ impl From<crate::R<IN_ERR_EOF_DES_ADDR_CH0_SPEC>> for R {
         R(reader)
     }
 }
-#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH0` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
-pub type IN_ERR_EOF_DES_ADDR_CH0_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
+pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader<u32, u32>;
 impl R {
     #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
     #[inline(always)]
-    pub fn in_err_eof_des_addr_ch0(&self) -> IN_ERR_EOF_DES_ADDR_CH0_R {
-        IN_ERR_EOF_DES_ADDR_CH0_R::new(self.bits)
+    pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R {
+        IN_ERR_EOF_DES_ADDR_R::new(self.bits)
     }
 }
 #[doc = "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_err_eof_des_addr_ch0](index.html) module"]