tell cargo about all our custom cfgs

esp-hal/Cargo.toml

@@ -188,4 +188,4 @@ ci = ["async", "embedded-hal-02", "embedded-io", "ufmt", "defmt", "bluetooth", "
 mixed_attributes_style = "allow"
 
 [lints.rust]
-unexpected_cfgs = "allow"
+unexpected_cfgs = { level = "warn", check-cfg = ['cfg(host_os, values("windows"))'] }

esp-hal/src/interrupt/riscv.rs

@@ -15,10 +15,8 @@
 pub use esp_riscv_rt::TrapFrame;
 use riscv::register::{mcause, mtvec};
 
-#[cfg(not(any(plic, clic)))]
+#[cfg(not(plic))]
 pub use self::classic::*;
-#[cfg(clic)]
-pub use self::clic::*;
 #[cfg(plic)]
 pub use self::plic::*;
 pub use self::vectored::*;
@@ -140,41 +138,27 @@ pub enum Priority {
     /// Priority level 7.
     Priority7,
     /// Priority level 8.
-    #[cfg(not(clic))]
     Priority8,
     /// Priority level 9.
-    #[cfg(not(clic))]
     Priority9,
     /// Priority level 10.
-    #[cfg(not(clic))]
     Priority10,
     /// Priority level 11.
-    #[cfg(not(clic))]
     Priority11,
     /// Priority level 12.
-    #[cfg(not(clic))]
     Priority12,
     /// Priority level 13.
-    #[cfg(not(clic))]
     Priority13,
     /// Priority level 14.
-    #[cfg(not(clic))]
     Priority14,
     /// Priority level 15.
-    #[cfg(not(clic))]
     Priority15,
 }
 
 impl Priority {
     /// Maximum interrupt priority
     pub const fn max() -> Priority {
-        cfg_if::cfg_if! {
-            if #[cfg(not(clic))] {
-                Priority::Priority15
-            } else {
-                Priority::Priority7
-            }
-        }
+        Priority::Priority15
     }
 
     /// Minimum interrupt priority
@@ -560,7 +544,7 @@ mod vectored {
     interrupt_handler!(19);
 }
 
-#[cfg(not(any(plic, clic)))]
+#[cfg(not(plic))]
 mod classic {
     use super::{CpuInterrupt, InterruptKind, Priority};
     use crate::Cpu;
@@ -809,126 +793,3 @@ mod plic {
             .write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8));
     }
 }
-
-#[cfg(clic)]
-mod clic {
-    use super::{CpuInterrupt, InterruptKind, Priority};
-    use crate::Cpu;
-
-    pub(super) const DISABLED_CPU_INTERRUPT: u32 = 0;
-
-    pub(super) const EXTERNAL_INTERRUPT_OFFSET: u32 = 16;
-
-    pub(super) const PRIORITY_TO_INTERRUPT: &[usize] =
-        &[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
-
-    pub(super) const INTERRUPT_TO_PRIORITY: &[usize] =
-        &[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
-
-    // The memory map for interrupt registers is on a per-core basis,
-    // base points to the current core interrupt register,
-    // whereas base + DUALCORE_CLIC_CTRL_OFF points to the other
-    // core registers, regardless of the core we are currently running on.
-
-    const DR_REG_CLIC_CTRL_BASE: u32 = 0x20801000;
-    const DUALCORE_CLIC_CTRL_OFF: u32 = 0x10000;
-
-    const CLIC_EXT_INTR_NUM_OFFSET: usize = 16;
-
-    bitfield::bitfield! {
-        #[derive(Clone, Copy, Default)]
-        pub struct InterruptControl(u32);
-
-        bool,pending, set_pending: 0;
-        bool,enabled, set_enabled: 8;
-        bool,vectored, set_vectored: 16;
-        u8,trigger, set_trigger: 18, 17;
-        u8,mode, _: 23, 22;
-        u8,priority, set_priority: 31, 29;
-    }
-
-    /// Get pointer to interrupt control register for the given core and CPU
-    /// interrupt number
-    fn intr_cntrl(core: Cpu, cpu_interrupt_number: usize) -> *mut u32 {
-        let offset = if core == crate::get_core() {
-            0
-        } else {
-            DUALCORE_CLIC_CTRL_OFF
-        };
-        unsafe {
-            ((DR_REG_CLIC_CTRL_BASE + offset) as *mut u32)
-                .add(CLIC_EXT_INTR_NUM_OFFSET + cpu_interrupt_number)
-        }
-    }
-
-    /// Enable a CPU interrupt on current core
-    ///
-    /// # Safety
-    ///
-    /// Make sure there is an interrupt handler registered.
-    pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
-        let cpu_interrupt_number = which as usize;
-        let intr_cntrl = intr_cntrl(crate::get_core(), cpu_interrupt_number);
-        unsafe {
-            let mut val = InterruptControl(intr_cntrl.read_volatile());
-            val.set_enabled(true);
-            intr_cntrl.write_volatile(val.0);
-        }
-    }
-
-    /// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
-    ///
-    /// The vectored interrupt handler will take care of clearing edge interrupt
-    /// bits.
-    pub fn set_kind(core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
-        let cpu_interrupt_number = which as usize;
-        unsafe {
-            let intr_cntrl = intr_cntrl(core, cpu_interrupt_number);
-            let mut val = InterruptControl(intr_cntrl.read_volatile());
-            val.set_trigger(match kind {
-                InterruptKind::Level => 0b00,
-                InterruptKind::Edge => 0b10,
-            });
-            intr_cntrl.write_volatile(val.0);
-        }
-    }
-
-    /// Set the priority level of an CPU interrupt
-    ///
-    /// # Safety
-    ///
-    /// Great care must be taken when using this function; avoid changing the
-    /// priority of interrupts 1 - 15.
-    pub unsafe fn set_priority(core: Cpu, which: CpuInterrupt, priority: Priority) {
-        let cpu_interrupt_number = which as usize;
-        let intr_cntrl = intr_cntrl(core, cpu_interrupt_number);
-        unsafe {
-            let mut val = InterruptControl(intr_cntrl.read_volatile());
-            val.set_priority(priority as u8);
-            intr_cntrl.write_volatile(val.0);
-        }
-    }
-
-    /// Clear a CPU interrupt
-    #[inline]
-    pub fn clear(core: Cpu, which: CpuInterrupt) {
-        let cpu_interrupt_number = which as usize;
-        unsafe {
-            let intr_cntrl = intr_cntrl(core, cpu_interrupt_number);
-            let mut val = InterruptControl(intr_cntrl.read_volatile());
-            val.set_pending(false);
-            intr_cntrl.write_volatile(val.0);
-        }
-    }
-
-    /// Get interrupt priority
-    #[inline]
-    pub(super) fn get_priority_by_core(core: Cpu, cpu_interrupt: CpuInterrupt) -> Priority {
-        let cpu_interrupt_number = cpu_interrupt as usize;
-        unsafe {
-            let intr_cntrl = intr_cntrl(core, cpu_interrupt_number);
-            let val = InterruptControl(intr_cntrl.read_volatile());
-            core::mem::transmute::<u8, Priority>(val.priority())
-        }
-    }
-}

esp-hal/src/system.rs

@@ -304,9 +304,7 @@ pub struct SoftwareInterruptControl {
     pub software_interrupt1: SoftwareInterrupt<1>,
     /// Software interrupt 2.
     pub software_interrupt2: SoftwareInterrupt<2>,
-    /// Software interrupt 3 (only available when not running on a multi-core
-    /// system with the `embassy` feature enabled).
-    #[cfg(not(all(feature = "embassy", multi_core)))]
+    /// Software interrupt 3.
     pub software_interrupt3: SoftwareInterrupt<3>,
 }
 
@@ -316,10 +314,6 @@ impl SoftwareInterruptControl {
             software_interrupt0: SoftwareInterrupt {},
             software_interrupt1: SoftwareInterrupt {},
             software_interrupt2: SoftwareInterrupt {},
-            // the thread-executor uses SW-INT3 when used on a multi-core system
-            // we cannot easily require `software_interrupt3` there since it's created
-            // before `main` via proc-macro so we  cfg it away from users
-            #[cfg(not(all(feature = "embassy", multi_core)))]
             software_interrupt3: SoftwareInterrupt {},
         }
     }

esp-metadata/src/lib.rs

@@ -1,6 +1,7 @@
 //! Metadata for Espressif devices, primarily intended for use in build scripts.
 
 use anyhow::{bail, Result};
+use strum::IntoEnumIterator;
 
 const ESP32_TOML: &str = include_str!("../devices/esp32.toml");
 const ESP32C2_TOML: &str = include_str!("../devices/esp32c2.toml");
@@ -231,9 +232,24 @@ impl Config {
 
     /// Define all symbols for a given configuration.
     pub fn define_symbols(&self) {
+        define_all_possible_symbols();
         // Define all necessary configuration symbols for the configured device:
         for symbol in self.all() {
             println!("cargo:rustc-cfg={symbol}");
         }
     }
 }
+
+/// Defines all possible symbols that _could_ be output from this crate
+/// regardless of the chosen configuration.
+///
+/// This is required to avoid triggering the unexpected-cfgs lint.
+fn define_all_possible_symbols() {
+    for chip in Chip::iter() {
+        let config = Config::for_chip(&chip);
+        for symbol in config.all() {
+            // https://doc.rust-lang.org/cargo/reference/build-scripts.html#rustc-check-cfg
+            println!("cargo:rustc-check-cfg=cfg({})", symbol);
+        }
+    }
+}

hil-test/Cargo.toml

@@ -236,6 +236,3 @@ incremental      = false
 opt-level        = 3
 lto              = "fat"
 overflow-checks  = false
-
-[lints.rust]
-unexpected_cfgs = "allow"