PeripheralRef/spi (#299)

* Add missing UART instances * Add SPI to list of peripherals to be created * Refactor SPI driver to use PeripheralRef
esp-rs · Dec 13, 2022 · cfe8382 · cfe8382
1 parent 2632421
commit cfe8382
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Showing 7 changed files with 107 additions and 88 deletions.
diff --git a/esp-hal-common/src/cpu_control/esp32.rs b/esp-hal-common/src/cpu_control/esp32.rs
@@ -137,7 +137,7 @@ impl CpuControl {
     }
 
     fn enable_cache(&mut self, core: Cpu) {
-        let spi0 = unsafe { &(*crate::pac::SPI0::ptr()) };
+        let spi0 = unsafe { &(*crate::peripherals::SPI0::ptr()) };
 
         let dport_control = crate::pac::DPORT::PTR;
         let dport_control = unsafe { &*dport_control };

diff --git a/esp-hal-common/src/peripherals/esp32.rs b/esp-hal-common/src/peripherals/esp32.rs
@@ -54,5 +54,10 @@ mod peripherals {
     crate::create_peripherals! {
         UART0,
         UART1,
+        UART2,
+        SPI0,
+        SPI1,
+        SPI2,
+        SPI3,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32c2.rs b/esp-hal-common/src/peripherals/esp32c2.rs
@@ -36,5 +36,8 @@ mod peripherals {
     crate::create_peripherals! {
         UART0,
         UART1,
+        SPI0,
+        SPI1,
+        SPI2,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32c3.rs b/esp-hal-common/src/peripherals/esp32c3.rs
@@ -47,5 +47,8 @@ mod peripherals {
     crate::create_peripherals! {
         UART0,
         UART1,
+        SPI0,
+        SPI1,
+        SPI2,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32s2.rs b/esp-hal-common/src/peripherals/esp32s2.rs
@@ -52,5 +52,10 @@ mod peripherals {
     crate::create_peripherals! {
         UART0,
         UART1,
+        SPI0,
+        SPI1,
+        SPI2,
+        SPI3,
+        SPI4,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32s3.rs b/esp-hal-common/src/peripherals/esp32s3.rs
@@ -63,5 +63,10 @@ mod peripherals {
     crate::create_peripherals! {
         UART0,
         UART1,
+        UART2,
+        SPI0,
+        SPI1,
+        SPI2,
+        SPI3,
     }
 }