Clear AFIFOs before transfers

esp-rs · May 23, 2024 · a9a5d9b · a9a5d9b
1 parent c19e6f7
commit a9a5d9b
Showing 1 changed file with 18 additions and 0 deletions.
diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs
@@ -852,6 +852,15 @@ where
                 .bit(is_high_part)
         });
 
+        self.spi.register_block().dma_conf().modify(|_, w| {
+            w.rx_afifo_rst()
+                .set_bit()
+                .buf_afifo_rst()
+                .set_bit()
+                .dma_afifo_rst()
+                .set_bit()
+        });
+
         self.spi.start_operation();
 
         Ok(FifoTransfer { spi: self, fifo })
@@ -3217,6 +3226,15 @@ pub trait Instance: private::Sealed {
 
         self.configure_datalen(data_len as u32 * 8);
 
+        self.register_block().dma_conf().modify(|_, w| {
+            w.rx_afifo_rst()
+                .set_bit()
+                .buf_afifo_rst()
+                .set_bit()
+                .dma_afifo_rst()
+                .set_bit()
+        });
+
         self.start_operation();
     }