Erase gpio types by default

esp-hal/src/gpio/mod.rs

@@ -276,7 +276,10 @@ pub trait Pin: private::Sealed {
     /// This converts pin singletons (`GpioPin<0>`, …), which are all different
     /// types, into the same type. It is useful for creating arrays of pins,
     /// or avoiding generics.
-    fn degrade(self) -> ErasedPin where Self: Sized {
+    fn degrade(self) -> ErasedPin
+    where
+        Self: Sized,
+    {
         self.degrade_internal(private::Internal)
     }
 
@@ -1872,18 +1875,34 @@ macro_rules! touch_common {
 }
 
 /// GPIO output driver.
-pub struct Output<'d, P> {
+pub struct Output<'d, P = ErasedPin> {
     pin: Flex<'d, P>,
 }
 
+impl<'d> Output<'d> {
+    /// Create GPIO output driver for a [GpioPin] with the provided level
+    #[inline]
+    pub fn new<P: OutputPin>(
+        pin: impl crate::peripheral::Peripheral<P = P> + 'd,
+        initial_output: Level,
+    ) -> Self {
+        let pin = Flex::new(pin);
+
+        Self::new_inner(pin, initial_output)
+    }
+}
+
 impl<'d, P> Output<'d, P>
 where
     P: OutputPin,
 {
     /// Create GPIO output driver for a [GpioPin] with the provided level
     #[inline]
-    pub fn new(pin: impl crate::peripheral::Peripheral<P = P> + 'd, initial_output: Level) -> Self {
-        let pin = Flex::new(pin);
+    pub fn new_typed(
+        pin: impl crate::peripheral::Peripheral<P = P> + 'd,
+        initial_output: Level,
+    ) -> Self {
+        let pin = Flex::new_typed(pin);
 
         Self::new_inner(pin, initial_output)
     }
@@ -1946,19 +1965,33 @@ where
 }
 
 /// GPIO input driver.
-pub struct Input<'d, P> {
+pub struct Input<'d, P = ErasedPin> {
     pin: Flex<'d, P>,
 }
 
+impl<'d> Input<'d> {
+    /// Create GPIO input driver for a [Pin] with the provided [Pull]
+    /// configuration.
+    #[inline]
+    pub fn new<P: InputPin>(
+        pin: impl crate::peripheral::Peripheral<P = P> + 'd,
+        pull: Pull,
+    ) -> Self {
+        let pin = Flex::new(pin);
+
+        Self::new_inner(pin, pull)
+    }
+}
+
 impl<'d, P> Input<'d, P>
 where
     P: InputPin,
 {
     /// Create GPIO input driver for a [Pin] with the provided [Pull]
     /// configuration.
     #[inline]
-    pub fn new(pin: impl crate::peripheral::Peripheral<P = P> + 'd, pull: Pull) -> Self {
-        let pin = Flex::new(pin);
+    pub fn new_typed(pin: impl crate::peripheral::Peripheral<P = P> + 'd, pull: Pull) -> Self {
+        let pin = Flex::new_typed(pin);
 
         Self::new_inner(pin, pull)
     }
@@ -2020,24 +2053,38 @@ where
 }
 
 /// GPIO open-drain output driver.
-pub struct OutputOpenDrain<'d, P> {
+pub struct OutputOpenDrain<'d, P = ErasedPin> {
     pin: Flex<'d, P>,
 }
 
+impl<'d> OutputOpenDrain<'d> {
+    /// Create GPIO open-drain output driver for a [Pin] with the provided
+    /// initial output-level and [Pull] configuration.
+    #[inline]
+    pub fn new<P: InputPin + OutputPin>(
+        pin: impl crate::peripheral::Peripheral<P = P> + 'd,
+        initial_output: Level,
+        pull: Pull,
+    ) -> Self {
+        let pin = Flex::new(pin);
+
+        Self::new_inner(pin, initial_output, pull)
+    }
+}
+
 impl<'d, P> OutputOpenDrain<'d, P>
 where
     P: InputPin + OutputPin,
 {
     /// Create GPIO open-drain output driver for a [Pin] with the provided
     /// initial output-level and [Pull] configuration.
     #[inline]
-    pub fn new(
+    pub fn new_typed(
         pin: impl crate::peripheral::Peripheral<P = P> + 'd,
         initial_output: Level,
         pull: Pull,
-    ) -> Self
-    {
-        let pin = Flex::new(pin);
+    ) -> Self {
+        let pin = Flex::new_typed(pin);
 
         Self::new_inner(pin, initial_output, pull)
     }
@@ -2130,18 +2177,29 @@ where
 }
 
 /// Flexible pin driver.
-pub struct Flex<'d, P> {
+pub struct Flex<'d, P = ErasedPin> {
     pin: PeripheralRef<'d, P>,
 }
 
+impl<'d> Flex<'d> {
+    /// Create flexible pin driver for a [Pin].
+    /// No mode change happens.
+    #[inline]
+    pub fn new<P: Pin>(pin: impl crate::peripheral::Peripheral<P = P> + 'd) -> Self {
+        crate::into_ref!(pin);
+        let pin = pin.degrade_internal(private::Internal);
+        Self::new_typed(pin)
+    }
+}
+
 impl<'d, P> Flex<'d, P>
 where
     P: Pin,
 {
     /// Create flexible pin driver for a [Pin].
     /// No mode change happens.
     #[inline]
-    pub fn new(pin: impl crate::peripheral::Peripheral<P = P> + 'd) -> Self {
+    pub fn new_typed(pin: impl crate::peripheral::Peripheral<P = P> + 'd) -> Self {
         crate::into_ref!(pin);
         Self { pin }
     }

hil-test/tests/gpio.rs

@@ -65,8 +65,8 @@ mod tests {
         esp_hal_embassy::init(&clocks, timg0.timer0);
 
         Context {
-            io2: Input::new(io.pins.gpio2, Pull::Down),
-            io3: Output::new(io.pins.gpio3, Level::Low),
+            io2: Input::new_typed(io.pins.gpio2, Pull::Down),
+            io3: Output::new_typed(io.pins.gpio3, Level::Low),
             delay,
         }
     }

hil-test/tests/qspi_read.rs

@@ -42,14 +42,14 @@ cfg_if::cfg_if! {
 struct Context {
     spi: esp_hal::peripherals::SPI2,
     dma_channel: Channel<'static, DmaChannel0, Blocking>,
-    miso: esp_hal::gpio::GpioPin<2>,
-    miso_mirror: Output<'static, GpioPin<3>>,
+    miso: GpioPin<2>,
+    miso_mirror: Output<'static>,
     clocks: Clocks<'static>,
 }
 
 fn execute(
     mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>,
-    mut miso_mirror: Output<'static, GpioPin<3>>,
+    mut miso_mirror: Output<'static>,
     wanted: u8,
 ) {
     const DMA_BUFFER_SIZE: usize = 4;

hil-test/tests/qspi_write_read.rs

@@ -44,14 +44,14 @@ cfg_if::cfg_if! {
 struct Context {
     spi: esp_hal::peripherals::SPI2,
     dma_channel: Channel<'static, DmaChannel0, Blocking>,
-    mosi: esp_hal::gpio::GpioPin<2>,
-    mosi_mirror: Output<'static, GpioPin<3>>,
+    mosi: GpioPin<2>,
+    mosi_mirror: Output<'static>,
     clocks: Clocks<'static>,
 }
 
 fn execute(
     mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>,
-    mut mosi_mirror: Output<'static, GpioPin<3>>,
+    mut mosi_mirror: Output<'static>,
     wanted: u8,
 ) {
     const DMA_BUFFER_SIZE: usize = 4;

hil-test/tests/spi_full_duplex_dma_async.rs

@@ -57,7 +57,7 @@ const DMA_BUFFER_SIZE: usize = 5;
 struct Context {
     spi: SpiDmaBus<'static, SPI2, DmaChannel0, FullDuplexMode, Async>,
     pcnt_unit: Unit<'static, 0>,
-    out_pin: Output<'static, GpioPin<5>>,
+    out_pin: Output<'static>,
     mosi_mirror: GpioPin<2>,
 }
 

hil-test/tests/spi_full_duplex_dma_pcnt.rs

@@ -51,7 +51,7 @@ cfg_if::cfg_if! {
 struct Context {
     spi: SpiDma<'static, SPI2, DmaChannel0, FullDuplexMode, Blocking>,
     pcnt_unit: Unit<'static, 0>,
-    out_pin: Output<'static, GpioPin<5>>,
+    out_pin: Output<'static>,
     mosi_mirror: GpioPin<2>,
 }
 

hil-test/tests/spi_half_duplex_read.rs

@@ -16,7 +16,7 @@
 use esp_hal::{
     dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
     dma_buffers,
-    gpio::{GpioPin, Io, Level, Output},
+    gpio::{Io, Level, Output},
     peripherals::SPI2,
     prelude::*,
     spi::{
@@ -42,7 +42,7 @@ cfg_if::cfg_if! {
 
 struct Context {
     spi: SpiDma<'static, SPI2, DmaChannel0, HalfDuplexMode, Blocking>,
-    miso_mirror: Output<'static, GpioPin<3>>,
+    miso_mirror: Output<'static>,
 }
 
 #[cfg(test)]