Update CH422G and add a new example

[Lzw655]

• Closes Added the OC pin usage of CH422G #7
• Closes New Waveshare (b) devices use Different CH422G outputs  #5

[ThermIQ]

Hi,
I believe there is a bug in this code with regards to output control of OC0-OC3. These outputs can either be push-pull OR Open Collector. Open Collector is selected by setting corresponding bit in the control register. The specific bit is bit4.

As the english datasheat for Ch422G is likely the worst I've seen in my 40 years of electronic design it took me considerable time, a chinese friend and some magic smoke to figure this out.

The full register map looks like this:

    //
    // Bit:        |    7    |  6  |  5  |    4    |    3    |    2    |    1     |    0    |
    //             |   ---   | --- | --- |   ---   | ------- | ------- | -------- | ------- |
    // Value:      | [SLEEP] |  /  |  /  | [OD_EN] |         |[A_SCAN] |          | [IO_OE] |
    //             |   ---   | --- | --- |   ---   | ------- | ------- | -------- | ------- |
    // Default:    |    0    |  0  |  0  |   0     |    0    |    0    |    0     |    1    |

This is described in the datasheet CH422G datasheet in paragraph 6.1.2

The testcase provided likely works since the electric interface accepts push-pull and the Open Collector drive is not verified as high-Z on 1-as output

[Lzw655]

Hi @ThermIQ,

Thank you for your feedback!

At first, I designed the OC0-OC3 open-drain function (OD_EN: bit 4) according to the CH422G datasheet, but @H-sw123 found through hardware testing that this feature didn’t work and pointed out that the CH422G datasheet was incorrect. The correct data bit sequence is the one used in the current driver.

Additionally, the driver code in ESPHome is also worth referencing.

[ThermIQ]

Ok, I will try to verify the OpenCollector function later. I'm not the least surprised that the datasheet is wrong