StarFive JH7100 Clock Generator Driver

[geertu]

This is a preliminary driver (incl. DT bindings) for the StarFive JH7100 Clock Generator, which is part of the PCR (Power/Clock/Reset) Management Unit.

For now, all clocks are implemented as fixed-factor clocks relative to osc0, based on the list of fixed-frequency clocks defined in jh7100.dtsi. To be updated with the real clock topology and with actual clock register accesses when the documentation becomes available.

[pdp7]

Thanks, this boots successfully on my board

[pdp7]

@geertu do you think it makes sense for me to add clocks to the gpio yaml?

diff --git a/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml b/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
index 8c9d14d9ac3b..f623d8b1fbf0 100644
--- a/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
@@ -34,6 +34,9 @@ properties:
   "#interrupt-cells":
     const: 2
 
+  clocks:
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -42,6 +45,7 @@ required:
   - "#interrupt-cells"
   - "#gpio-cells"
   - gpio-controller
+  - clocks
 
 additionalProperties: false
 
@@ -55,6 +59,7 @@ examples:
         interrupt-controller;
         #interrupt-cells = <2>;
         interrupts = <32>;
+        clocks = < NOT SURE WHAT TO PUT HERE >;
       };

[pdp7]

I am thinking GPIO is using clk_apb1_bus:


so it looks like it would be:

#define JH7100_CLK_APB1		<br class="Apple-interchange-newline">

and thus:

diff --git a/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml b/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
index 8c9d14d9ac3b..f623d8b1fbf0 100644
--- a/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
@@ -34,6 +34,9 @@ properties:
   "#interrupt-cells":
     const: 2
 
+  clocks:
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -42,6 +45,7 @@ required:
   - "#interrupt-cells"
   - "#gpio-cells"
   - gpio-controller
+  - clocks
 
 additionalProperties: false
 
@@ -55,6 +59,7 @@ examples:
         interrupt-controller;
         #interrupt-cells = <2>;
         interrupts = <32>;
+        clocks = <&clkgen JH7100_CLK_APB1>;
       };

[geertu]

@pdp7

so it looks like it would be:

#define JH7100_CLK_APB1		<br class="Apple-interchange-newline">

and thus:

diff --git a/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml b/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
index 8c9d14d9ac3b..f623d8b1fbf0 100644
--- a/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/starfive,jh7100-gpio.yaml
@@ -34,6 +34,9 @@ properties:
   "#interrupt-cells":
     const: 2
 
+  clocks:
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -42,6 +45,7 @@ required:
   - "#interrupt-cells"
   - "#gpio-cells"
   - gpio-controller
+  - clocks
 
 additionalProperties: false
 
@@ -55,6 +59,7 @@ examples:
         interrupt-controller;
         #interrupt-cells = <2>;
         interrupts = <32>;
+        clocks = <&clkgen JH7100_CLK_APB1>;
       };

Yes, you could do that. But currently the GPIO driver doesn't use this clock. The only use I can see is for power management.
While we do know GPIO is clocked by APB1, we do not know yet whether it is clocked directly (always-on), or if the clock supply can be gated, through a (to be implemented) gateable child clock of APB1.
I wouldn't be surprised if the "PCR (Power/Clock/Reset) Management Unit" would provide invididual gateable clocks for each module, which would bring us to power-domains and Runtime PM. Probably the PMR provides individual resets for each module, too.

Any chance we can get full documentation for the PMR block? Thanks!

[pdp7]

@geertu sorry for the delay, I have created
starfive-tech/JH7100_Docs#15

I will use that to followup with starfive

[pdp7]

@geertu this now temporary documentation for clock and reset. I will still followup about power domains