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Add Platform Agnostic TM Query #3846

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May 15, 2019
Merged

Add Platform Agnostic TM Query #3846

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7c6ddd3
Change absolute include to relative
May 13, 2019
0193bf0
Add Platform Agnostic TM Query
May 13, 2019
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6 changes: 6 additions & 0 deletions compiler/env/OMRCPU.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,12 @@ class CPU
bool isI386() { return _minorArch == TR::m_arch_i386; }
bool isAMD64() { return _minorArch == TR::m_arch_amd64; }

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This API should have the same Doxygen comment as the platform-specific ones. It is the API used by architectures that don't have TM support yet (e.g., ARM32, AArch64).

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Good point, missed that

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Updated (see https://github.com/eclipse/omr/compare/9142f82165c1480c850be7146abc18c6ecc4fd46..0193bf0dfe329515a899e6ef22c35ef6fcae37ec)

/** @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
*
* @return false; this is the default answer unless overridden by an extending class.
*/
bool supportsTransactionalMemoryInstructions() { return false; }

private:
TR_Processor _processor;

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6 changes: 6 additions & 0 deletions compiler/p/env/OMRCPU.cpp
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Expand Up @@ -33,6 +33,12 @@ OMR::Power::CPU::getPPCis64bit()
return (p >= TR_FirstPPC64BitProcessor)? true : false;
}

bool
OMR::Power::CPU::supportsTransactionalMemoryInstructions()
{
return self()->getPPCSupportsTM();
}

bool
OMR::Power::CPU::isTargetWithinIFormBranchRange(intptrj_t targetAddress, intptrj_t sourceAddress)
{
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7 changes: 7 additions & 0 deletions compiler/p/env/OMRCPU.hpp
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Expand Up @@ -65,6 +65,13 @@ class CPU : public OMR::CPU
bool getPPCSupportsTM() { return false; }
bool getPPCSupportsLM() { return false; }

/** @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
* Alias of getPPCSupportsTM() as a platform agnostic query.
*
* @return true if TM is available, false otherwise.
*/
bool supportsTransactionalMemoryInstructions();

/**
* @brief Provides the maximum forward branch displacement in bytes reachable
* with an I-Form branch instruction.
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8 changes: 8 additions & 0 deletions compiler/x/env/OMRCPU.cpp
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Expand Up @@ -24,6 +24,7 @@
#include "env/CPU.hpp"
#include "env/JitConfig.hpp"
#include "env/ProcessorInfo.hpp"
#include "infra/Flags.hpp"
#include "x/runtime/X86Runtime.hpp"


Expand Down Expand Up @@ -112,3 +113,10 @@ OMR::X86::CPU::testOSForSSESupport()
{
return false;
}

bool
OMR::X86::CPU::supportsTransactionalMemoryInstructions()
{
flags32_t processorFeatureFlags8(self()->getX86ProcessorFeatureFlags8());
return processorFeatureFlags8.testAny(TR_RTM);
}
7 changes: 7 additions & 0 deletions compiler/x/env/OMRCPU.hpp
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Expand Up @@ -64,6 +64,13 @@ class CPU : public OMR::CPU

bool testOSForSSESupport();


/** @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
*
* @return true if TM is available, false otherwise.
*/
bool supportsTransactionalMemoryInstructions();

/**
* @brief Answers whether the distance between a target and source address
* is within the reachable RIP displacement range.
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10 changes: 8 additions & 2 deletions compiler/z/env/OMRCPU.cpp
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Expand Up @@ -27,7 +27,7 @@
#pragma csect(STATIC,"OMRZCPUBase#S")
#pragma csect(TEST,"OMRZCPUBase#T")

#include "compiler/z/env/OMRCPU.hpp"
#include "env/CPU.hpp"

const char*
OMR::Z::CPU::getProcessorName(int32_t machineId)
Expand Down Expand Up @@ -207,6 +207,12 @@ OMR::Z::CPU::getSupportsTransactionalMemoryFacility()
return _flags.testAny(S390SupportsTM);
}

bool
OMR::Z::CPU::supportsTransactionalMemoryInstructions()
{
return self()->getSupportsTransactionalMemoryFacility();
}


bool
OMR::Z::CPU::setSupportsTransactionalMemoryFacility(bool value)
Expand Down Expand Up @@ -375,4 +381,4 @@ OMR::Z::CPU::isTargetWithinBranchRelativeRILRange(intptrj_t targetAddress, intpt
{
return (targetAddress == sourceAddress + ((intptrj_t)((int32_t)((targetAddress - sourceAddress) / 2))) * 2) &&
(targetAddress % 2 == 0);
}
}
6 changes: 6 additions & 0 deletions compiler/z/env/OMRCPU.hpp
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Expand Up @@ -122,6 +122,12 @@ class CPU : public OMR::CPU
* Determines whether the Transactional Memory (TM) facility is available on the current processor.
*/
bool getSupportsTransactionalMemoryFacility();

/** \brief
* Determines whether the Transactional Memory (TM) facility is available on the current processor.
* Alias of getSupportsTransactionalMemoryFacility() as a platform agnostic query.
*/
bool supportsTransactionalMemoryInstructions();

/** \brief
* Determines whether the Transactional Memory (TM) facility is available on the current processor.
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