WIP: AArch64: Add support for ARM64 in Debug.cpp

This commit adds some more code for aarch64 in the common Debug.cpp
and related files.

Signed-off-by: knn-k <[email protected]>

compiler/aarch64/CMakeLists.txt

@@ -21,6 +21,26 @@
 
 compiler_library(aarch64
 # Target files
+	${CMAKE_CURRENT_LIST_DIR}/codegen/ARM64BinaryEncoding.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/ARM64Debug.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/ARM64Instruction.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/ARM64OutOfLineCodeSection.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/ARM64SystemLinkage.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/BinaryEvaluator.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/ControlFlowEvaluator.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/FPTreeEvaluator.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/GenerateInstructions.cpp
 	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRCodeGenerator.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRInstruction.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRLinkage.cpp
 	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRMachine.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRMemoryReference.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRRealRegister.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRRegisterDependency.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRRegisterIterator.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRSnippet.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OMRTreeEvaluator.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/OpBinary.cpp
+	${CMAKE_CURRENT_LIST_DIR}/codegen/UnaryEvaluator.cpp
+	${CMAKE_CURRENT_LIST_DIR}/env/OMRDebugEnv.cpp
 )

compiler/aarch64/env/OMRDebugEnv.cpp

@@ -0,0 +1,30 @@
+/*******************************************************************************
+ * Copyright (c) 2018, 2018 IBM Corp. and others
+ *
+ * This program and the accompanying materials are made available under
+ * the terms of the Eclipse Public License 2.0 which accompanies this
+ * distribution and is available at http://eclipse.org/legal/epl-2.0
+ * or the Apache License, Version 2.0 which accompanies this distribution
+ * and is available at https://www.apache.org/licenses/LICENSE-2.0.
+ *
+ * This Source Code may also be made available under the following Secondary
+ * Licenses when the conditions for such availability set forth in the
+ * Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
+ * version 2 with the GNU Classpath Exception [1] and GNU General Public
+ * License, version 2 with the OpenJDK Assembly Exception [2].
+ *
+ * [1] https://www.gnu.org/software/classpath/license.html
+ * [2] http://openjdk.java.net/legal/assembly-exception.html
+ *
+ * SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
+ *******************************************************************************/
+
+#include "env/DebugEnv.hpp"
+
+OMR::ARM64::DebugEnv::DebugEnv() :
+      OMR::DebugEnv()
+   {
+   _hexAddressWidthInChars = 16;
+   _hexAddressFieldWidthInChars = 18;
+   _codeByteColumnWidth = 10;
+   }

compiler/aarch64/env/OMRDebugEnv.hpp

@@ -44,6 +44,10 @@ namespace ARM64
 
 class OMR_EXTENSIBLE DebugEnv : public OMR::DebugEnv
    {
+public:
+
+   DebugEnv();
+
    };
 
 }

compiler/ras/Debug.cpp

@@ -751,14 +751,14 @@ TR_Debug::printPrefix(TR::FILE *pOutFile, TR::Instruction *instr, uint8_t *curso
       char *p0 = prefix;
       char *p1 = prefix + strlen(prefix);
 
-      // Print machine code in bytes on X86, in words on PPC,ARM
+      // Print machine code in bytes on X86, in words on PPC,ARM,ARM64
       // Stop if we try to run over the buffer.
       if (TR::Compiler->target.cpu.isX86())
          {
          for (int i = 0; i < size && p1 - p0 + 3 < prefixWidth; i++, p1 += 3)
             sprintf(p1, " %02x", *cursor++);
          }
-      else if (TR::Compiler->target.cpu.isPower() || TR::Compiler->target.cpu.isARM())
+      else if (TR::Compiler->target.cpu.isPower() || TR::Compiler->target.cpu.isARM() || TR::Compiler->target.cpu.isARM64())
          {
          for (int i = 0; i < size && p1 - p0 + 9 < prefixWidth; i += 4, p1 += 9, cursor += 4)
             sprintf(p1, " %08x", *((uint32_t *)cursor));
@@ -2870,6 +2870,14 @@ TR_Debug::print(TR::FILE *pOutFile, TR::GCRegisterMap * map)
       }
 #endif
 
+#if defined(TR_TARGET_ARM64)
+   if (TR::Compiler->target.cpu.isARM64())
+      {
+      printARM64GCRegisterMap(pOutFile, map);
+      return;
+      }
+#endif
+
    }
 
 void
@@ -2998,6 +3006,10 @@ TR_Debug::getName(TR::Register *reg, TR_RegisterSizes size)
 #if defined(TR_TARGET_S390)
       if (TR::Compiler->target.cpu.isZ())
          return getName(toRealRegister(reg), size);
+#endif
+#if defined(TR_TARGET_ARM64)
+      if (TR::Compiler->target.cpu.isARM64())
+         return getName((TR::RealRegister *)reg, size);
 #endif
       TR_ASSERT(0, "TR_Debug::getName() ==> unknown target platform for given real register\n");
       }
@@ -3173,6 +3185,13 @@ TR_Debug::print(TR::FILE *pOutFile, TR::Register * reg, TR_RegisterSizes size)
          print(pOutFile, toRealRegister(reg), size);
          return;
          }
+#endif
+#if defined(TR_TARGET_ARM64)
+      if (TR::Compiler->target.cpu.isARM64())
+         {
+         print(pOutFile, (TR::RealRegister *)reg, size);
+         return;
+         }
 #endif
       }
    else