[bazel] allocate 5 cores per verilator test to allow for harness and …

…overhead An alternative to lowRISC#16913 to prevent harnesses from getting pre-empted by a simulation load. Signed-off-by: Drew Macrae <[email protected]>
drewmacrae · Dec 22, 2022 · e99a6f2 · e99a6f2
1 parent 42ab42b
commit e99a6f2
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/rules/opentitan_test.bzl b/rules/opentitan_test.bzl
@@ -152,7 +152,7 @@ def verilator_params(
         "@//hw:verilator",
         "@//hw:fusesoc_ignore",
     ]
-    required_tags = ["verilator", "cpu:4"]
+    required_tags = ["verilator", "cpu:5"]
     kwargs.update(
         args = default_args + args,
         data = required_data + data,