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JIT ARM64-SVE: Add BS_1A, BT_1A #99458

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merged 5 commits into from
Mar 11, 2024
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amanasifkhalid
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Part of #94549.

cstool output:

and   z0.b, z0.b, #0xAA
and   z1.b, z1.b, #0xAA
and   z2.h, z2.h, #0xFF00
and   z3.h, z3.h, #0xFF00
eor   z4.s, z4.s, #0x3FFC000
eor   z5.s, z5.s, #0x3FFC000
orr   z6.d, z6.d, #0xFFFFF000000000
orr   z7.d, z7.d, #0xFFFFF000000000
dupm  z0.b, #0x70
mov   z1.h, #0x3FFC
dupm  z2.s, #0x7000
mov   z3.d, #0xFFFFFFFFFFFF0000
dupm  z4.b, #0x3F
dupm  z5.h, #0x700
mov   z6.s, #0xFFFFF0
mov   z7.d, #0xFFFFF00000FFFFFF

JitDisasm output:

and     z0.b, z0.b, #170
and     z1.b, z1.b, #170
and     z2.h, z2.h, #0xFF00
and     z3.h, z3.h, #0xFF00
eor     z4.s, z4.s, #0x3FFC000
eor     z5.s, z5.s, #0x3FFC000
orr     z6.d, z6.d, #0xfffff000000000
orr     z7.d, z7.d, #0xfffff000000000
dupm    z0.b, #112
mov     z1.h, #0x3FFC
dupm    z2.s, #0x7000
mov     z3.d, #-0x10000
dupm    z4.b, #63
dupm    z5.h, #0x700
mov     z6.s, #0xFFFFF0
mov     z7.d, #0xfffff00000ffffff

The JIT has some slightly different logic for printing immediates, but that seems to be the only difference between the outputs. cc @dotnet/arm64-contrib.

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Mar 8, 2024
@amanasifkhalid amanasifkhalid added the arm-sve Work related to arm64 SVE/SVE2 support label Mar 8, 2024
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

@@ -376,6 +376,8 @@ enum insScalableOpts : unsigned

INS_SCALABLE_OPTS_WITH_VECTOR_PAIR, // Variants with {<Zn1>.<T>, <Zn2>.<T>} sve register pair (eg splice)

INS_SCALABLE_OPTS_IMM_BITMASK, // Variants with an immediate that is a bitmask
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This may not be the cleanest interface, but if we want to avoid creating new insScalableOpts entries, we could have the caller to emitIns_* always use INS_sve_dupm, and then rely on emitIns to use useMovDisasmForBitMask to decide which disasm should be used. But that might be confusing from the caller's perspective if we cannot pass INS_sve_mov.

@BruceForstall
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mov z6.s, #0xFFFFF0
mov z7.d, #0xfffff00000ffffff

Does the JIT print 32-bit immediates with upper case and 64-bit with lower case? It should at least be consistent.

@amanasifkhalid
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Does the JIT print 32-bit immediates with upper case and 64-bit with lower case? It should at least be consistent.

In emitter::emitDispImm, we always print 32-bit immediates with upper case. We only print 64-bit immediates with upper case if the immediate is an address offset; else, we print them with lower case. I'm not sure what the historic motivation for this is...

@BruceForstall
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In emitter::emitDispImm, we always print 32-bit immediates with upper case. We only print 64-bit immediates with upper case if the immediate is an address offset; else, we print them with lower case. I'm not sure what the historic motivation for this is...

Odd. I don't remember either.

@amanasifkhalid
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Odd. I don't remember either.

Would you like me to get rid of it, and always print immediates with upper case?

@BruceForstall
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Would you like me to get rid of it, and always print immediates with upper case?

IMO, everything in one case would be better (upper I guess is fine). But it certainly shouldn't be done for this PR, and it might not be worth putting time into it at all?

@amanasifkhalid amanasifkhalid merged commit 9f0a327 into dotnet:main Mar 11, 2024
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@amanasifkhalid amanasifkhalid deleted the bs_1a branch March 11, 2024 23:19
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