Add Arm64 encodings for SVE_DD_2A & SVE_DG_2A

[SwapnilGaikwad]

These groups emit predicated version of pfirst, rdffr & rdffrs instructions.

This clr output matches the one from capstone.

...
pfirst p0.b, p15, p0.b
rdffr p10.b, p15/z
rdffrs p7.b, p14/z
...

Contribute towards #94549.

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Issue Details

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These groups emit predicated version of pfirst, rdffr & rdffrs instructions.

This clr output matches the one from capstone.

...
pfirst p0.b, p15, p0.b
rdffr p10.b, p15/z
rdffrs p7.b, p14/z
...

Contribute towards #94549.

Author:	SwapnilGaikwad
Assignees:	-
Labels:	area-CodeGen-coreclr
Milestone:	-

[SwapnilGaikwad]

@a74nh @kunalspathak @dotnet/arm64-contrib

[kunalspathak]

This should be always PREDICATE_NONE for DD_2A, right? https://docsmirror.github.io/A64/2023-06/pfirst_p_p_p.html

[SwapnilGaikwad]

It needs PREDICATE_NONE for the second reg only else we will miss the element type on remaining predicate registers. It would cause the following diff with capstone.

- pfirst p0.b, p15, p0.b
+ pfirst p0, p15, p0

[TIHan]

@kunalspathak , this was one of the reasons why insGetPredicateType was originally called something like insGetReg2PredicateType.

Because pfirst has two predicate registers, insGetPredicateType is ambiguous of what it should return.

[TIHan]

I just now noticed the regPos was added. That seems to clear up any ambiguity.

[kunalspathak]

right...having regPos is better.

[kunalspathak]

From https://docsmirror.github.io/A64/2023-06/rdffr_p_p_f.html, this should be:

case IF_SVE_DG_2A:
   return ((regpos == 2) ? PREDICATE_ZERO: PREDICATE_NONE);

[SwapnilGaikwad]

Sure, it would avoid asserts and make IF_SVE_DG_2A a separate case for groups that have only two registers and those are predicate registers. The other groups also have only two predicate registers but they have non-predicated registers as well.

[SwapnilGaikwad]

oh, and we need PREDICATE_SIZED for reg1 otherwise we won't get the element type in <Pd>.B.

[kunalspathak]

LGTM. Thanks!

[TIHan]

LGTM, pretty straightforward.