Update the bit field of encoding function names #96082
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@dotnet/arm64-contrib @a74nh @SwapnilGaikwad |
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LGTM! |
src/coreclr/jit/emitarm64.cpp
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| /*static*/ emitter::code_t emitter::insEncodeReg_R_18_to_17(regNumber reg) | ||
| /*static*/ emitter::code_t emitter::insEncodeReg_R_17_to_16(regNumber reg) | ||
| { | ||
| assert(isIntegerRegister(reg)); | ||
| emitter::code_t ureg = (emitter::code_t)reg; | ||
| assert((ureg >= 0) && (ureg <= 32)); |
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| assert((ureg >= 0) && (ureg <= 32)); | |
| assert((ureg >= 0) && (ureg <= 3)); |
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psel uses this encoding and I am not sure what register represents by 2 bits. The manual says "Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field.". @a74nh do you know?
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PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
It's the Wv in the above. That's quite an odd instruction encoding - it's trying to fit in 4 registers, a 5bit immediate and the element size.
It's not explicitly mentioned, but w12 would be 00, w13 would be 01, etc
So, the assert should be (ureg >= 12) && (ureg <= 15).
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hoping to get it address in #95996 to skip a CI run.
The arm manual parsing tool had a bug where I was not taking into account the extra space, resulting in function names off by 1. Renamed the function names.