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[RISC-V] Fix GitHub_* tests #88640

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merged 4 commits into from
Jul 16, 2023
Merged

[RISC-V] Fix GitHub_* tests #88640

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6cce004
[RISC-V] Fix GitHub_17585 test failure
clamp03 Jul 10, 2023
3c69208
[RISC-V] Fix GitHub_23147 test failure
clamp03 Jul 11, 2023
31053db
[RISC-V] Remove lvIsHfaRegArg assertion
clamp03 Jul 12, 2023
c6c0b9f
[RISC-V] Update
clamp03 Jul 14, 2023
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24 changes: 19 additions & 5 deletions src/coreclr/jit/codegenriscv64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6510,12 +6510,19 @@ void CodeGen::genJmpMethod(GenTree* jmp)
{
var_types loadType = TYP_UNDEF;

// NOTE for RISCV64: not supports the HFA.
assert(!varDsc->lvIsHfaRegArg());
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HFA is ARM only concept. I think this assert isn't needed.

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Removed. Thank you.

if (varTypeIsStruct(varDsc))
{
// Must be <= 16 bytes or else it wouldn't be passed in registers, except for HFA,
// which can be bigger (and is handled above).
noway_assert(EA_SIZE_IN_BYTES(varDsc->lvSize()) <= 16);
loadType = varDsc->GetLayout()->GetGCPtrType(0);
if (emitter::isFloatReg(argReg))
{
loadType = varDsc->lvIs4Field1 ? TYP_FLOAT : TYP_DOUBLE;
}
else
loadType = varDsc->GetLayout()->GetGCPtrType(0);
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}
else
{
Expand All @@ -6532,14 +6539,21 @@ void CodeGen::genJmpMethod(GenTree* jmp)
regSet.AddMaskVars(genRegMask(argReg));
gcInfo.gcMarkRegPtrVal(argReg, loadType);

if (compiler->lvaIsMultiregStruct(varDsc, compiler->info.compIsVarArgs))
if (varDsc->GetOtherArgReg() < REG_STK)
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It's code from LA64, when I made genJmpMethod() implementation, I've took ARM64 version since it's more clear. E.g. what's the meaning of if (varDsc->GetOtherArgReg() < REG_STK)?

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Because ARM64 and RISCV have different calling convention. Right, ARM64 seems more clearer, but RISCV follows LA64's. So we need to update like LA64.
GetOtherArgReg is the second register for multi argument register for RISCV and LA64.

In case of ARM64 in the test, it passes two float register arguments using one int register (REG_A0). So compiler->lvaIsMultiregStruct returns false. In method prolog in a callee, it makes two float values from REG_A0 in ARM64.

{
// Restore the second register.
argRegNext = genRegArgNext(argReg);
argRegNext = varDsc->GetOtherArgReg();

if (emitter::isFloatReg(argRegNext))
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And why special case for float is need?

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Because it cannot get the exact type by using varDsc->GetLayout()->GetGCPtrType(1) (only returns TYP_I_IMPL for all primitive and non-gc value type) and GetEmitter()->emitIns_R_S needs the exact type for the arguments.

If you want to update calling convention like ARM64, we can do. However, I think it is better to investigate after RISC-V is stable.

{
loadType = varDsc->lvIs4Field2 ? TYP_FLOAT : TYP_DOUBLE;
}
else
loadType = varDsc->GetLayout()->GetGCPtrType(1);
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loadType = varDsc->GetLayout()->GetGCPtrType(1);
loadSize = emitActualTypeSize(loadType);
GetEmitter()->emitIns_R_S(ins_Load(loadType), loadSize, argRegNext, varNum, TARGET_POINTER_SIZE);
int offs = loadSize == EA_4BYTE ? 4 : 8;
GetEmitter()->emitIns_R_S(ins_Load(loadType), loadSize, argRegNext, varNum, offs);

regSet.AddMaskVars(genRegMask(argRegNext));
gcInfo.gcMarkRegPtrVal(argRegNext, loadType);
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31 changes: 14 additions & 17 deletions src/coreclr/vm/riscv64/virtualcallstubcpu.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -82,8 +82,7 @@ struct DispatchStub
private:
friend struct DispatchHolder;

DWORD _entryPoint[9];
DWORD _pad;
DWORD _entryPoint[8];
size_t _expectedMT;
PCODE _implTarget;
PCODE _failTarget;
Expand All @@ -102,30 +101,28 @@ struct DispatchHolder
void Initialize(DispatchHolder* pDispatchHolderRX, PCODE implTarget, PCODE failTarget, size_t expectedMT)
{
// auipc t4,0
// addi t4, t4, 36
// ld t0,0(a0) ; methodTable from object in $a0
// ld t6,0(t4) // t6 _expectedMT
// bne t6, t0, failLabel
// ld t4, 8(t4) // t4 _implTarget
// ld t0, 0(a0) // methodTable from object in $a0
// ld t6, 32(t4) // t6 _expectedMT
// bne t6, t0, failLabel
// ld t4, 40(t4) // t4 _implTarget
// jalr x0, t4, 0
// failLabel:
// ld t4, 16(t4) // t4 _failTarget
// ld t4, 48(t4) // t4 _failTarget
// jalr x0, t4, 0
//
//
// _expectedMT
// _implTarget
// _failTarget

_stub._entryPoint[0] = DISPATCH_STUB_FIRST_DWORD; // auipc t4,0 // 0x00000e97
_stub._entryPoint[1] = 0x028e8e93; // addi t4, t4, 40
_stub._entryPoint[2] = 0x00053283; // ld t0, 0(a0) //; methodTable from object in $a0
_stub._entryPoint[3] = 0x000ebf83; // ld r6, 0(t4) // t6 _expectedMT
_stub._entryPoint[4] = 0x005f9663; // bne t6, t0, failLabel
_stub._entryPoint[5] = 0x008ebe83; // ld t4, 8(t4) // t4 _implTarget
_stub._entryPoint[6] = 0x000e8067; // jalr x0, t4, 0
_stub._entryPoint[7] = 0x010ebe83; // ld t4, 16(t4) // t4 _failTarget
_stub._entryPoint[8] = 0x000e8067; // jalr x0, t4, 0
_stub._entryPoint[0] = DISPATCH_STUB_FIRST_DWORD; // auipc t4,0 // 0x00000e97
_stub._entryPoint[1] = 0x00053283; // ld t0, 0(a0) // methodTable from object in $a0
_stub._entryPoint[2] = 0x020ebf83; // ld t6, 32(t4) // t6 _expectedMT
_stub._entryPoint[3] = 0x005f9663; // bne t6, t0, failLabel
_stub._entryPoint[4] = 0x028ebe83; // ld t4, 40(t4) // t4 _implTarget
_stub._entryPoint[5] = 0x000e8067; // jalr x0, t4, 0
_stub._entryPoint[6] = 0x030ebe83; // ld t4, 48(t4) // t4 _failTarget
_stub._entryPoint[7] = 0x000e8067; // jalr x0, t4, 0

_stub._expectedMT = expectedMT;
_stub._implTarget = implTarget;
Expand Down