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Optimization on LinearScan::buildPhysRegRecords #83862

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Apr 1, 2023
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8 changes: 5 additions & 3 deletions src/coreclr/jit/lsrabuild.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1876,6 +1876,10 @@ const unsigned lsraRegOrderSize = ArrLen(lsraRegOrder);
// TODO-XARCH-AVX512 we might want to move this to be configured with the rbm variables too
static const regNumber lsraRegOrderFlt[] = {REG_VAR_ORDER_FLT};
const unsigned lsraRegOrderFltSize = ArrLen(lsraRegOrderFlt);
#if defined(TARGET_AMD64)
static const regNumber lsraRegOrderFltUpper[] = {REG_VAR_ORDER_FLT_UPPER};
const unsigned lsraRegOrderUpperFltSize = ArrLen(lsraRegOrderFltUpper);
#endif // TARGET_AMD64

//------------------------------------------------------------------------
// buildPhysRegRecords: Make an interval for each physical register
Expand All @@ -1902,13 +1906,11 @@ void LinearScan::buildPhysRegRecords()
#if defined(TARGET_AMD64)
if (compiler->canUseEvexEncoding())
{
const regNumber lsraRegOrderFltUpper[] = {REG_VAR_ORDER_FLT_UPPER};
const unsigned lsraRegOrderUpperFltSize = ArrLen(lsraRegOrderFltUpper);
for (unsigned int i = 0; i < lsraRegOrderUpperFltSize; i++)
{
regNumber reg = lsraRegOrderFltUpper[i];
RegRecord* curr = &physRegs[reg];
curr->regOrder = (unsigned char)(i + lsraRegOrderUpperFltSize);
curr->regOrder = (unsigned char)(i + lsraRegOrderFltSize);
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}
}
#endif // TARGET_AMD64
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