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#78303 Add transformation ~v1 & v2 to VectorXxx.AndNot(v1, v2) #81993

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45 changes: 45 additions & 0 deletions src/coreclr/jit/gentree.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -24073,6 +24073,51 @@ void GenTreeHWIntrinsic::SetHWIntrinsicId(NamedIntrinsic intrinsicId)
(op1->GetAuxiliaryType() == op2->GetAuxiliaryType()) && (op1->GetOtherReg() == op2->GetOtherReg()) &&
OperandsAreEqual(op1, op2);
}

genTreeOps GenTreeHWIntrinsic::HWOperGet()
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{
switch (GetHWIntrinsicId())
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@tannergooding do you think we can then (not necessarily in this PR) add this to the table where intrinsics are defined?

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We should be able to do so, yes.

However, I rather think we'd want to represent it just a little bit differently to avoid bloating the metadata tables given most intrinsics end up as none.

{
#if defined(TARGET_XARCH)
case NI_SSE_And:
case NI_SSE2_And:
case NI_AVX_And:
case NI_AVX2_And:
#elif defined(TARGET_ARM64)
case NI_AdvSimd_And:
#endif
{
return GT_AND;
}

#if defined(TARGET_ARM64)
case NI_AdvSimd_Not:
{
return GT_NOT;
}
#endif

#if defined(TARGET_XARCH)
case NI_SSE_Xor:
case NI_SSE2_Xor:
case NI_AVX_Xor:
case NI_AVX2_Xor:
#elif defined(TARGET_ARM64)
case NI_AdvSimd_Xor:
#endif
{
return GT_XOR;
}

// TODO: Handle other cases

default:
{
return GT_NONE;
}
}
}

#endif // FEATURE_HW_INTRINSICS

//---------------------------------------------------------------------------------------
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2 changes: 2 additions & 0 deletions src/coreclr/jit/gentree.h
Original file line number Diff line number Diff line change
Expand Up @@ -6410,6 +6410,8 @@ struct GenTreeHWIntrinsic : public GenTreeJitIntrinsic

static bool Equals(GenTreeHWIntrinsic* op1, GenTreeHWIntrinsic* op2);

genTreeOps HWOperGet();

private:
void SetHWIntrinsicId(NamedIntrinsic intrinsicId);

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91 changes: 91 additions & 0 deletions src/coreclr/jit/morph.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -10869,7 +10869,98 @@ GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)
INDEBUG(node->gtDebugFlags |= GTF_DEBUG_NODE_MORPHED);
return node;
}
default:
{
break;
}
}

// Transforms:
// 1.(~v1 & v2) to VectorXxx.AndNot(v1, v2)
// 2.(v1 & (~v2)) to VectorXxx.AndNot(v2, v1)
switch (node->HWOperGet())
{
case GT_AND:
{
GenTree* op1 = node->Op(1);
GenTree* op2 = node->Op(2);
GenTree* lhs = nullptr;
GenTree* rhs = nullptr;

if (op1->OperIsHWIntrinsic())
{
// Try handle: ~op1 & op2
GenTreeHWIntrinsic* hw = op1->AsHWIntrinsic();
genTreeOps hwOper = hw->HWOperGet();

if (hwOper == GT_NOT)
{
lhs = op1;
rhs = op2;
}
else if (hwOper == GT_XOR)
{
GenTree* hwOp1 = hw->Op(1);
GenTree* hwOp2 = hw->Op(2);

if (hwOp1->IsVectorAllBitsSet())
{
lhs = hwOp2;
rhs = op2;
}
else if (hwOp2->IsVectorAllBitsSet())
{
lhs = hwOp1;
rhs = op2;
}
}
}

if ((lhs == nullptr) && op2->OperIsHWIntrinsic())
{
// Try handle: op1 & ~op2
GenTreeHWIntrinsic* hw = op2->AsHWIntrinsic();
genTreeOps hwOper = hw->HWOperGet();

if (hwOper == GT_NOT)
{
lhs = op1;
rhs = op2;
}
else if (hwOper == GT_XOR)
{
GenTree* hwOp1 = hw->Op(1);
GenTree* hwOp2 = hw->Op(2);

if (hwOp1->IsVectorAllBitsSet())
{
lhs = op1;
rhs = hwOp2;
}
else if (hwOp2->IsVectorAllBitsSet())
{
lhs = op1;
rhs = hwOp1;
}
}
}

if (lhs == nullptr || rhs == nullptr)
{
break;
}

var_types simdType = node->TypeGet();
CorInfoType simdBaseJitType = node->GetSimdBaseJitType();
unsigned int simdSize = node->GetSimdSize();

GenTree* andnNode = gtNewSimdBinOpNode(GT_AND_NOT, simdType, lhs, rhs, simdBaseJitType, simdSize, true);

DEBUG_DESTROY_NODE(node);
INDEBUG(andnNode->gtDebugFlags |= GTF_DEBUG_NODE_MORPHED);

return andnNode;
}
default:
{
break;
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