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Refactoring store liveness update #80539

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merged 7 commits into from
Mar 1, 2023
Merged

Refactoring store liveness update #80539

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1a73a73
Unifying var desc and liveness update on storeLclFld/Var
BrianBohe Dec 15, 2022
b565b67
Updating varDsc home after spill and refactoring
BrianBohe Dec 15, 2022
436e138
Adding back function comment
BrianBohe Feb 8, 2023
4097cf7
Merge branch 'main' into refactoring_store_liveness_update
BrianBohe Feb 16, 2023
a83fbbe
Forcing inline of store update on liveness
BrianBohe Feb 22, 2023
e274d12
Fixing format
BrianBohe Feb 22, 2023
6b782b3
Merge remote-tracking branch 'ms/main' into refactoring_store_livenes…
BrianBohe Feb 28, 2023
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24 changes: 24 additions & 0 deletions src/coreclr/jit/codegen.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1026,6 +1026,30 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#endif // !defined(TARGET_64BIT)

//-------------------------------------------------------------------------
// genUpdateLifeStore: Do liveness udpate after tree store instructions
// were emitted, update result var's home if it was stored on stack.
//
// Arguments:
// tree - Gentree node
// targetReg - of the tree
// varDsc - result value's variable
//
// Return Value:
// None.
__forceinline void genUpdateLifeStore(GenTree* tree, regNumber targetReg, LclVarDsc* varDsc)
{
if (targetReg != REG_NA)
{
genProduceReg(tree);
}
else
{
genUpdateLife(tree);
varDsc->SetRegNum(REG_STK);
}
}

// Do liveness update for register produced by the current node in codegen after
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// code has been emitted for it.
void genProduceReg(GenTree* tree);
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9 changes: 2 additions & 7 deletions src/coreclr/jit/codegenarm.cpp
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Expand Up @@ -1116,19 +1116,14 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* tree)

emitter* emit = GetEmitter();
emit->emitIns_S_R(ins, attr, dataReg, varNum, /* offset */ 0);

// Updating variable liveness after instruction was emitted
genUpdateLife(tree);

varDsc->SetRegNum(REG_STK);
}
else // store into register (i.e move into register)
{
// Assign into targetReg when dataReg (from op1) is not the same register
inst_Mov(targetType, targetReg, dataReg, /* canSkip */ true);

genProduceReg(tree);
}

genUpdateLifeStore(tree, targetReg, varDsc);
}
}
}
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25 changes: 6 additions & 19 deletions src/coreclr/jit/codegenarm64.cpp
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Expand Up @@ -2928,7 +2928,6 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
if (targetReg != REG_NA)
{
emit->emitIns_R_I(INS_movi, emitActualTypeSize(targetType), targetReg, 0x00, INS_OPTS_16B);
genProduceReg(lclNode);
}
else
{
Expand All @@ -2941,8 +2940,8 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
assert(targetType == TYP_SIMD8);
GetEmitter()->emitIns_S_R(INS_str, EA_8BYTE, REG_ZR, varNum, 0);
}
genUpdateLife(lclNode);
}
genUpdateLifeStore(lclNode, targetReg, varDsc);
return;
}
if (zeroInit)
Expand Down Expand Up @@ -2971,18 +2970,13 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
emitAttr attr = emitActualTypeSize(targetType);

emit->emitIns_S_R(ins, attr, dataReg, varNum, /* offset */ 0);

genUpdateLife(lclNode);

varDsc->SetRegNum(REG_STK);
}
else // store into register (i.e move into register)
{
// Assign into targetReg when dataReg (from op1) is not the same register
inst_Mov(targetType, targetReg, dataReg, /* canSkip */ true);

genProduceReg(lclNode);
}
genUpdateLifeStore(lclNode, targetReg, varDsc);
}
}

Expand Down Expand Up @@ -5266,8 +5260,9 @@ void CodeGen::genStoreLclTypeSimd12(GenTreeLclVarCommon* treeNode)
{
assert(treeNode->OperIs(GT_STORE_LCL_FLD, GT_STORE_LCL_VAR));

unsigned offs = treeNode->GetLclOffs();
unsigned varNum = treeNode->GetLclNum();
unsigned offs = treeNode->GetLclOffs();
unsigned varNum = treeNode->GetLclNum();
LclVarDsc* varDsc = compiler->lvaGetDesc(varNum);
assert(varNum < compiler->lvaCount);

GenTree* data = treeNode->gtGetOp1();
Expand All @@ -5285,8 +5280,6 @@ void CodeGen::genStoreLclTypeSimd12(GenTreeLclVarCommon* treeNode)

// Update life after instruction emitted
genUpdateLife(treeNode);

LclVarDsc* varDsc = compiler->lvaGetDesc(varNum);
varDsc->SetRegNum(REG_STK);

return;
Expand All @@ -5301,20 +5294,14 @@ void CodeGen::genStoreLclTypeSimd12(GenTreeLclVarCommon* treeNode)
assert(GetEmitter()->isVectorRegister(tgtReg));

inst_Mov(treeNode->TypeGet(), tgtReg, dataReg, /* canSkip */ true);
genProduceReg(treeNode);
}
else
{
// Need an additional integer register to extract upper 4 bytes from data.
regNumber tmpReg = treeNode->GetSingleTempReg();
GetEmitter()->emitStoreSimd12ToLclOffset(varNum, offs, dataReg, tmpReg);

// Update life after instruction emitted
genUpdateLife(treeNode);

LclVarDsc* varDsc = compiler->lvaGetDesc(varNum);
varDsc->SetRegNum(REG_STK);
}
genUpdateLifeStore(treeNode, tgtReg, varDsc);
}

#endif // FEATURE_SIMD
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23 changes: 2 additions & 21 deletions src/coreclr/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4931,17 +4931,7 @@ void CodeGen::genCodeForStoreLclFld(GenTreeLclFld* tree)
{
GetEmitter()->emitInsBinary(ins_Store(targetType), emitTypeSize(tree), tree, op1);
}

// Updating variable liveness after instruction was emitted
if (targetReg != REG_NA)
{
genProduceReg(tree);
}
else
{
genUpdateLife(tree);
varDsc->SetRegNum(REG_STK);
}
genUpdateLifeStore(tree, targetReg, varDsc);
}

//------------------------------------------------------------------------
Expand Down Expand Up @@ -5060,16 +5050,7 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
emitTypeSize(targetType));
}
}
// Updating variable liveness after instruction was emitted
if (targetReg != REG_NA)
{
genProduceReg(lclNode);
}
else
{
genUpdateLife(lclNode);
varDsc->SetRegNum(REG_STK);
}
genUpdateLifeStore(lclNode, targetReg, varDsc);
}
}

Expand Down
14 changes: 5 additions & 9 deletions src/coreclr/jit/simdcodegenxarch.cpp
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Expand Up @@ -236,16 +236,16 @@ void CodeGen::genStoreLclTypeSimd12(GenTreeLclVarCommon* treeNode)
GenTree* data = treeNode->Data();
assert(!data->isContained());

regNumber tgtReg = treeNode->GetRegNum();
regNumber dataReg = genConsumeReg(data);
regNumber tgtReg = treeNode->GetRegNum();
regNumber dataReg = genConsumeReg(data);
LclVarDsc* varDsc = compiler->lvaGetDesc(varNum);

if (tgtReg != REG_NA)
{
// Simply use mov if we move a SIMD12 reg to another SIMD12 reg
assert(genIsValidFloatReg(tgtReg));

inst_Mov(treeNode->TypeGet(), tgtReg, dataReg, /* canSkip */ true);
genProduceReg(treeNode);
}
else
{
Expand All @@ -272,13 +272,9 @@ void CodeGen::genStoreLclTypeSimd12(GenTreeLclVarCommon* treeNode)
// Store upper 4 bytes
emit->emitIns_S_R(INS_movss, EA_4BYTE, tmpReg, varNum, offs + 8);
}

// Update the life of treeNode
genUpdateLife(treeNode);

LclVarDsc* varDsc = compiler->lvaGetDesc(varNum);
varDsc->SetRegNum(REG_STK);
}

genUpdateLifeStore(treeNode, tgtReg, varDsc);
}

//-----------------------------------------------------------------------------
Expand Down