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Merge pull request eclipse-omr#862 from 0dvictor/SIMD
Introduce SIMD evaluators on X86
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,153 @@ | ||
| /******************************************************************************* | ||
| * | ||
| * (c) Copyright IBM Corp. 2017, 2017 | ||
| * | ||
| * This program and the accompanying materials are made available | ||
| * under the terms of the Eclipse Public License v1.0 and | ||
| * Apache License v2.0 which accompanies this distribution. | ||
| * | ||
| * The Eclipse Public License is available at | ||
| * http://www.eclipse.org/legal/epl-v10.html | ||
| * | ||
| * The Apache License v2.0 is available at | ||
| * http://www.opensource.org/licenses/apache2.0.php | ||
| * | ||
| * Contributors: | ||
| * Multiple authors (IBM Corp.) - initial implementation and documentation | ||
| *******************************************************************************/ | ||
|
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| #include "codegen/CodeGenerator.hpp" // for CodeGenerator, etc | ||
| #include "codegen/MemoryReference.hpp" | ||
| #include "codegen/TreeEvaluator.hpp" | ||
| #include "il/ILOpCodes.hpp" // for ILOpCodes, etc | ||
| #include "il/ILOps.hpp" // for ILOpCode | ||
| #include "il/Node.hpp" // for Node, etc | ||
| #include "il/Node_inlines.hpp" | ||
| #include "infra/Assert.hpp" // for TR_ASSERT | ||
| #include "x/codegen/X86Instruction.hpp" | ||
| #include "x/codegen/X86Ops.hpp" // for ::LABEL, ::JE4, etc | ||
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| namespace TR { class Instruction; } | ||
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| static TR::MemoryReference* ConvertToPatchableMemoryReference(TR::MemoryReference* mr, TR::Node* node, TR::CodeGenerator* cg) | ||
| { | ||
| if (mr->getSymbolReference().isUnresolved()) | ||
| { | ||
| // The load instructions may be wider than 8-bytes (our patching window) | ||
| // but we won't know that for sure until after register assignment. | ||
| // Hence, the unresolved memory reference must be evaluated into a register first. | ||
| // | ||
| TR::Register* tempReg = cg->allocateRegister(); | ||
| generateRegMemInstruction(LEARegMem(cg), node, tempReg, mr, cg); | ||
| mr = generateX86MemoryReference(tempReg, 0, cg); | ||
| cg->stopUsingRegister(tempReg); | ||
| } | ||
| return mr; | ||
| } | ||
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| TR::Register* OMR::X86::TreeEvaluator::SIMDRegLoadEvaluator(TR::Node* node, TR::CodeGenerator* cg) | ||
| { | ||
| TR::Register* globalReg = node->getRegister(); | ||
| if (!globalReg) | ||
| { | ||
| globalReg = cg->allocateRegister(TR_VRF); | ||
| node->setRegister(globalReg); | ||
| } | ||
| return globalReg; | ||
| } | ||
|
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| TR::Register* OMR::X86::TreeEvaluator::SIMDRegStoreEvaluator(TR::Node* node, TR::CodeGenerator* cg) | ||
| { | ||
| TR::Node* child = node->getFirstChild(); | ||
| TR::Register* globalReg = cg->evaluate(child); | ||
| cg->machine()->setXMMGlobalRegister(node->getGlobalRegisterNumber() - cg->machine()->getNumGlobalGPRs(), globalReg); | ||
| cg->decReferenceCount(child); | ||
| return globalReg; | ||
| } | ||
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| TR::Register* OMR::X86::TreeEvaluator::SIMDloadEvaluator(TR::Node* node, TR::CodeGenerator* cg) | ||
| { | ||
| TR::MemoryReference* tempMR = generateX86MemoryReference(node, cg); | ||
| tempMR = ConvertToPatchableMemoryReference(tempMR, node, cg); | ||
| TR::Register* resultReg = cg->allocateRegister(TR_VRF); | ||
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| TR_X86OpCodes opCode = BADIA32Op; | ||
| switch (node->getSize()) | ||
| { | ||
| case 16: | ||
| opCode = MOVDQURegMem; | ||
| break; | ||
| default: | ||
| if (cg->comp()->getOption(TR_TraceCG)) | ||
| traceMsg(cg->comp(), "Unsupported fill size: Node = %p\n", node); | ||
| TR_ASSERT(false, "Unsupported fill size"); | ||
| break; | ||
| } | ||
|
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| TR::Instruction* instr = generateRegMemInstruction(opCode, node, resultReg, tempMR, cg); | ||
| if (node->getOpCode().isIndirect()) | ||
| cg->setImplicitExceptionPoint(instr); | ||
| node->setRegister(resultReg); | ||
| tempMR->decNodeReferenceCounts(cg); | ||
| return resultReg; | ||
| } | ||
|
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| TR::Register* OMR::X86::TreeEvaluator::SIMDstoreEvaluator(TR::Node* node, TR::CodeGenerator* cg) | ||
| { | ||
| TR::Node* valueNode = node->getChild(node->getOpCode().isIndirect() ? 1 : 0); | ||
| TR::MemoryReference* tempMR = generateX86MemoryReference(node, cg); | ||
| tempMR = ConvertToPatchableMemoryReference(tempMR, node, cg); | ||
| TR::Register* valueReg = cg->evaluate(valueNode); | ||
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| TR_X86OpCodes opCode = BADIA32Op; | ||
| switch (node->getSize()) | ||
| { | ||
| case 16: | ||
| opCode = MOVDQUMemReg; | ||
| break; | ||
| default: | ||
| if (cg->comp()->getOption(TR_TraceCG)) | ||
| traceMsg(cg->comp(), "Unsupported fill size: Node = %p\n", node); | ||
| TR_ASSERT(false, "Unsupported fill size"); | ||
| break; | ||
| } | ||
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| TR::Instruction* instr = generateMemRegInstruction(opCode, node, tempMR, valueReg, cg); | ||
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| cg->decReferenceCount(valueNode); | ||
| tempMR->decNodeReferenceCounts(cg); | ||
| if (node->getOpCode().isIndirect()) | ||
| cg->setImplicitExceptionPoint(instr); | ||
| return NULL; | ||
| } | ||
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| TR::Register* OMR::X86::TreeEvaluator::SIMDsplatsEvaluator(TR::Node* node, TR::CodeGenerator* cg) | ||
| { | ||
| TR::Node* childNode = node->getChild(0); | ||
| TR::Register* childReg = cg->evaluate(childNode); | ||
|
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| uint8_t shufconst = 0; | ||
| switch (node->getDataType()) | ||
| { | ||
| case TR::VectorInt32: | ||
| case TR::VectorFloat: | ||
| shufconst = 0x00; // 00 00 00 00 shuffle xxxA to AAAA | ||
| break; | ||
| case TR::VectorInt64: | ||
| case TR::VectorDouble: | ||
| shufconst = 0x44; // 01 00 01 00 shuffle xxBA to BABA | ||
| break; | ||
| default: | ||
| if (cg->comp()->getOption(TR_TraceCG)) | ||
| traceMsg(cg->comp(), "Unsupported data type, Node = %p\n", node); | ||
| TR_ASSERT(false, "Unsupported data type"); | ||
| break; | ||
| } | ||
|
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| TR::Register* resultReg = cg->allocateRegister(TR_VRF); | ||
| generateRegRegImmInstruction(PSHUFDRegRegImm1, node, resultReg, childReg, shufconst, cg); | ||
|
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| node->setRegister(resultReg); | ||
| cg->decReferenceCount(childNode); | ||
| return resultReg; | ||
| } |
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