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LICENSE
LICENSE
 
 
README.md
README.md
 
 
apb_regs_top.sv
apb_regs_top.sv
 
 
axi_AR_allocator.sv
axi_AR_allocator.sv
 
 
axi_AW_allocator.sv
axi_AW_allocator.sv
 
 
axi_ArbitrationTree.sv
axi_ArbitrationTree.sv
 
 
axi_BR_allocator.sv
axi_BR_allocator.sv
 
 
axi_BW_allocator.sv
axi_BW_allocator.sv
 
 
axi_DW_allocator.sv
axi_DW_allocator.sv
 
 
axi_FanInPrimitive_Req.sv
axi_FanInPrimitive_Req.sv
 
 
axi_RR_Flag_Req.sv
axi_RR_Flag_Req.sv
 
 
axi_address_decoder_AR.sv
axi_address_decoder_AR.sv
 
 
axi_address_decoder_AW.sv
axi_address_decoder_AW.sv
 
 
axi_address_decoder_BR.sv
axi_address_decoder_BR.sv
 
 
axi_address_decoder_BW.sv
axi_address_decoder_BW.sv
 
 
axi_address_decoder_DW.sv
axi_address_decoder_DW.sv
 
 
axi_multiplexer.sv
axi_multiplexer.sv
 
 
axi_node.sv
axi_node.sv
 
 
axi_node_wrap.sv
axi_node_wrap.sv
 
 
axi_node_wrap_with_slices.sv
axi_node_wrap_with_slices.sv
 
 
axi_regs_top.sv
axi_regs_top.sv
 
 
axi_request_block.sv
axi_request_block.sv
 
 
axi_response_block.sv
axi_response_block.sv
 
 
defines.v
defines.v
 
 
src_files.yml
src_files.yml
 
 

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AXI Interconnect

This is an implementation of an AXI interconnect with configurable number of slave and master ports. The AXI interconnect supports multiple regions and allows runtime configuration of the memory map via AXI or APB.

It was written for the use in the PULP platform.

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  • SystemVerilog 98.7%
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