Improve x86 SIMD support #120
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powerjg
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Nov 14, 2023
Added a resource constraint, AtomicALUOperation, to GLC atomics performed in the TCC. The resource constraint uses a new class, ALUFreeList array. The class assumes the following: - There are a fixed number of atomic ALU pipelines - While a new cache line can be processed in each pipeline each cycle, if a cache line is currently going through a pipeline, it can't be processed again until it's finished Two configuration parameters have been used to tune this behavior: - tcc-num-atomic-alus corresponds to the number of atomic ALU pipelines - atomic-alu-latency corresponds to the latency of atomic ALU pipelines Change-Id: I25bdde7dafc3877590bb6536efdf57b8c540a939
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There are a huge number of x86 SIMD instructions.
Most are implemented in gem5 (though they haven't been tested).
However, they are generally microcoded and only work functionally.
It would be a great project to implement these instructions using the new vector register implementation in the CPU models.
E.g., https://gem5-review.googlesource.com/c/public/gem5/+/13519
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