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This enables the stdlib to load and run ELFie-based binaries See https://github.com/intel/pinball2elf for more details on ELFies Change-Id: Ic1b624df64da1c77afc0907257a9e989488912ec Signed-off-by: Jason Lowe-Power <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68038 Reviewed-by: Bobby Bruce <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
This adds a progress bar for downloading large files and computing md5sums on large files. Change-Id: Iddc9faf61e861837cc1e2e3b3dbdbeebd6ccf529 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67472 Tested-by: kokoro <[email protected]> Reviewed-by: Melissa Jost <[email protected]> Maintainer: Jason Lowe-Power <[email protected]>
AddressSanitizer found a new-delete-type-mismatch because of the custom new operator for DynInst. Adding a custom delete operator for DynInstPtr fixes this issue. It has been fixed the same way in Mozilla: https://bugzilla.mozilla.org/show_bug.cgi?id=1391500 Change-Id: I0ab4cb6d79cac88069cc2374a1deb499cdb15f02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68357 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
implementation We should create PLIC abstract and have common interface to let HiFive platform send and clear interrupt to variable type of PLIC Change-Id: Ic3a2ffc2a2a002540b400c70c85c3495fa838f2a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68197 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Yu-hsin Wang <[email protected]> Tested-by: kokoro <[email protected]>
This is basic abstract platform and all of RISC-V system should use platform inherit from HiFiveBase, HiFiveBase declared the common way to handle interrupt. Change-Id: I52122e1c82c200d7e6012433c2535c07d427f637 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68199 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Yu-hsin Wang <[email protected]> Tested-by: kokoro <[email protected]>
This piggy-backs on the writeOK method which already exists. It also modifies the flags returned as part of the memory's backdoor descriptor which doesn't enforce that the memory is read only, but will let the other party know it's expected not to write to it. Change-Id: Ib95e619c76c327d302e62a88515a92af11815981 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68557 Maintainer: Gabe Black <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Matthew Poremba <[email protected]>
While the PcCountTracker isn't necessary in the NULL ISA, the structure of the standard library requires us to have it built when running the replacement policy tests, which should fix these tests failing within the nightlies at the moment. Change-Id: I225b7923f2a11d351c24bdceba3ded4ed2b3bc87 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68597 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
This change adds relevant errors that allow building with gcc-13. Change-Id: Ib97a90ef647a9cd9ec1bf1f2bde61daca85de427 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68497 Maintainer: Bobby Bruce <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Bobby Bruce <[email protected]>
Change-Id: I2f089039c709fe4c3f7086263fb56470c7713bad Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68617 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Bobby Bruce <[email protected]>
This reverts commit 4b1c245 and commit 89c49d1 because they are causing the RISC-V Ubuntu boot test within the nightly tests to hang and time out. Change-Id: Ia4d8098ec940cb5900256c8cede0146256c851e5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68637 Tested-by: kokoro <[email protected]> Reviewed-by: Roger Chang <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]>
This summarizes a series of changes to move general Simple, Minor, O3 CPU stats to BaseCPU. This commit focuses on moving numBranches from SimpleCPU to the FetchCPUStats in the BaseCPU, and numFetchSuspends from MinorCPU into FetchCPUStats. More general information about this relation chain is below 1. Summary: Moved general CPU stats found across Simple, Minor, and O3 CPU models into BaseCPU through new stat groups. The stat groups are FetchCPUStats, ExecuteCPUStats, and CommitCPUStats. Implemented the committedControl stat vector found in MinorCPU for Simple and O3 CPU. Implemented the numStoreInsts stat found in SimpleCPU for O3CPU. IPC and CPI stats are now tracked at the core and thread level in BaseCPU and are made universal for simple, minor, o3, and kvm CPUs. Duplicate stats across the models are merged into a single stat in BaseCPU under the same stat name. This change does not implement every general level stat moved to BaseCPU for every model. 2. Stat API Changes a. SimpleCPU: statExecutedInstType vector unified into committedInstType numCondCtrlInsts unified into committedControl::isControl b. O3CPU: i. Fetch Stage branches in fetch unified into with numBranches rate renamed to fetchRate insts unified into with numInsts ii. Execute Stage Regfile stats unified into base with use of Simple's stat naming numRefs in IEW unified into numMemRefs numRate from IEW renamed to instRate iii. Commit Stage committedInsts is renamed to numInstsNotNOP committedOps is renamed to numOpsNotNOP instsCommitted is unified into numInsts opsCommitted is unified into numOps branches is unified into committedControl::isControl floating is unified into numFpInsts integer is unified into numIntInsts loads is unified into numLoadInsts memRefs is renamed to numMemRefs vectorInstructions is unified into numVecInsts 3. Details: Created three stat groups in BaseCPU. FetchCPUStats track statistics related to the fetch stage. ExecuteCPUStats track statistics related to the execute stage. CommitCPUStats track statistics related to the commit stage. There are three vectors in Base that store unique pointers to per thread instances of these stat groups. The stat group pointer for thread i is accessible at index i of one of these vectors. For example, stat numCCRegReads of the execute stage for thread 0 can be accessed with executeStats[0]->numCCRegReads. The stats.txt output will print the thread ID of the stat group. For example, numVecRegReads on thread 0 of a single core prints as "board.processor.cores.core.executeStats0.numVecRegReads". NOTE: Multithreading in gem5 is untested. Therefore per thread stats output in stats.txt is not currently guaranteed to be correctly formatted. For FetchCPUStats, the stats moved from SimpleCPU are numBranches and numInsts. From MinorCPU, the stat moved is numFetchSuspends. From O3CPU, the stats moved are from the O3 fetch stage: Stat branches is unified into numBranches, stat rate is renamed to fetchRate in Base, stat insts is unified into numInsts, stat icacheStallCycles keeps the same name in Base. For ExecuteCPUStats, the stats moved from SimpleCPU are dcacheStallCycles, numCCRegReads, numCCRegWrites, numFpAluAccesses, numFpRegReads, numFpRegWrites, numIntAluAccesses, numIntRegReads, numIntRegWrites, numMemRefs, numMiscRegReads, numMiscRegWrites, numVecAluAccesses, numVecPredRegReads, numVecPredRegWrites, numVecRegReads, numVecRegWrites. The stat moved from MinorCPU is numDiscardedOps. From O3, the Regfile stats in CPU are unified into the reg stats in Base and use the names found originally in SimpleCPU. From O3 IEW stage, numInsts keeps the same name in Base, numBranches is unified into numBranches in base, numNop keeps the same name in Base, numRefs is unified into numMemRefs in Base, numLoadInsts and numStoreInsts are moved into Base, numRate is renamed to instRate in base. For CommitCPUStats, the stats moved from SimpleCPU are numCondCtrlInsts, numFpInsts, numIntInsts, numLoadInsts, numStoreInsts, numVecInsts. The stats moved from MinorCPU are numInsts, committedInstType, and committedControl. statExecutedInstType of SimpleCPU is unified with committedInstType of MinorCPU. Implemented committedControl stats from MinorCPU in Simple and O3 CPU. In MinorCPU, this stat was a 2D vector, where the first dimension is the thread ID. In base it is now a 1D vector that is tied to a thread ID via the commitStats vector that the object is accessible through. From the O3 commit stage, committedInsts is renamed to numInstsNotNOP, committedOps is renamed to numOpsNotNOP, instsCommitted is unified into numInsts, opsCommitted is renamed to numOps, committedInstType is unified into committedInstType from Minor, branches is removed because it duplicates committedControl::IsControl, floating is unified into numFpInsts, interger is unified into numIntInsts, loads is unified into numLoadInsts, numStoreInsts is implemented for tracking in O3, memRefs is renamed to numMemRefs, vectorInstructions is unified into numVecInsts. Note that numCondCtrlInsts of Simple is unified into committedControl::IsCondCtrl. Implemented IPC and CPI tracking inside BaseCPU. In BaseCPU::BaseCPUStats, numInsts and numOps track per CPU core committed instructions and operations. In BaseCPU::FetchCPUStats, numInsts and numOps track per thread fetched instructions and operations. In BaseCPU::CommitCPUStats, numInsts tracks per thread executed instructions. In BaseCPU::CommitCPUStats, numInsts and numOps track per thread committed instructions and operations. In BaseSimpleCPU, the countInst() function has been split into countInst(), countFetchInst(), and countCommitInst(). The stat count incrementation step of countInst() has been removed and delegated to the other two functions. countFetchInst() increments numInsts and numOps of the FetchCPUStats group for a thread. countCommitInst() increments the numInsts and numOps of the CommitCPUStats group for a thread and of the BaseCPUStats group for a CPU core. These functions are called in the appropriate stage within timing.cc and atomic.cc. The call to countInst() is left unchanged. countFetchInst() is called in preExecute(). countCommitInst() is called in postExecute(). For MinorCPU, only the commit level numInsts and numOps stats have been implemented. IPC and CPI stats have been added to BaseCPUStats (core level) and CommitCPUStats (thread level). The formulas for the IPC and CPI stats in CommitCPUStats are set in the BaseCPU constructor, after the CommitCPUStats stat group object has been created. These replace IPC, CPI, totalIpc, and totalCpi stats in O3. Replaced committedInsts stats of KVM CPU with commitStats.numInsts of BaseCPU. This results in IPC and CPI printing in stats.txt for KVM simulations. This change does not implement most general stats found in one or two model for all others. Jira Ticket: https://gem5.atlassian.net/browse/GEM5-1304 Change-Id: I3c852f8dba3268c71b7a3415480fb63d8dc30cb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66031 Maintainer: Bobby Bruce <[email protected]> Reviewed-by: Bobby Bruce <[email protected]> Tested-by: kokoro <[email protected]>
Created stat group ExecuteCPUStats in BaseCPU and moved stats from the simple and minor cpu models. The stats moved from SimpleCPU are dcacheStallCycles, icacheStallCycles, numCCRegReads, numCCRegWrites, numFpAluAccesses, numFpRegReads, numFpRegWrites, numIntAluAccesses, numIntRegReads, numIntRegWrites, numMemRefs, numMiscRegReads, numMiscRegWrites, numVecAluAccesses, numVecPredRegReads, numVecPredRegWrites, numVecRegReads, numVecRegWrites. The stat moved from MinorCPU is numDiscardedOps. Also, ccRegfileReads, ccRegfileWrites, fpRegfileReads, fpRegfileWrites, intRegfileReads, intRegfileWrites, miscRegfileReads, miscRegfileWrites, vecPredRegfileReads, vecPredRegfileWrites, vecRegfileReads, and vecRegfileWrites are removed from cpu.hh and cpu.cc in O3CPU. The corresponding stats in BaseCPU::ExecuteCPUStats are used instead. Changed the getReg, getWritableReg, and setReg functions in the O3 CPU object to take the thread ID as a parameter. This is because the stats in base are stored in vectors that are indexed by thread ID. Change-Id: I801c5ceb4c70b7b281127569f11c6ee98f614b27 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67390 Maintainer: Bobby Bruce <[email protected]> Reviewed-by: Bobby Bruce <[email protected]> Tested-by: kokoro <[email protected]>
Created stat group CommitCPUStats in BaseCPU and moved stats from the simple cpu model. The stats moved from SImpleCPU are numCondCtrlInsts, numFpInsts, numIntInsts, numLoadInsts, numStoreInsts, numVecInsts. Moved committedControl of MinorCPU to BaseCPU::CommittedCPUStats. In MinorCPU, this stat was a 2D vector, where the first dimension is the thread ID. In base it is now a 1D vector that is tied to a thread ID via the commitStats vector. The committedControl stat vector in CommitCPUStats is updated in the same way in all CPU models. The function updateComCtrlStats will update committedControl and the CPU models will call this function instead of updating committedControl directly. This function takes a StaticInstPtr as input, which Simple, Minor, and O3 CPU models are able to provide. Removed stat "branches" from O3 commit stage. This stat duplicates BaseCPU::CommittedCPUStats::committedControl::IsControl. O3 commit stats floating, integer, loads, memRefs, vectorInstructions are replaced by numFpInsts, numIntInsts, numLoadInsts, numMemRefs, numVecInsts from BaseCPU::CommitCPUStats respectively. Implemented numStoreInsts from BaseCPU::commitCPUStats for O3 commit stage. Change-Id: I362cec51513a404de56a02b450d7663327be20f5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67391 Tested-by: kokoro <[email protected]> Maintainer: Bobby Bruce <[email protected]> Reviewed-by: Bobby Bruce <[email protected]>
In BaseCPU::BaseCPUStats, numInsts and numOps track per CPU core committed instructions and operations. In BaseCPU::FetchCPUStats, numInsts and numOps track per thread fetched instructions and operations. In BaseCPU::CommitCPUStats, numInsts and numOps track per thread committed instructions and operations. In BaseSimpleCPU, the countInst() function has been split into countInst(), countFetchInst(), and countCommitInst(). The stat count incrementation of countInst() has been removed and delegated to the other two functions. countFetchInst() increments numInsts and numOps of the FetchCPUStats group for a thread. countCommitInst() increments the numInsts and numOps of the CommitCPUStats group for a thread and of the BaseCPUStats group for a CPU core. These functions are called in the appropriate stage within timing.cc and atomic.cc. The call to countInst() is left unchanged. countFetchInst() is called in preExecute(). countCommitInst() is called in postExecute(). For MinorCPU, only the commit level numInsts and numOps stats have been implemented. IPC and CPI stats have been added to BaseCPUStats (core level) and CommitCPUStats (thread level). The formulas for the IPC and CPI stats in CommitCPUStats are set in the BaseCPU constructor, after the CommitCPUStats stat group object has been created. Change-Id: If893b331fe4a6908e4b4caf4a30f1b0aeb4c4266 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67392 Tested-by: kokoro <[email protected]> Reviewed-by: Bobby Bruce <[email protected]> Maintainer: Bobby Bruce <[email protected]>
Moved committedInsts from O3 cpu.* to BaseCPU as numInstsNotNOP because it tracks the instructions committed that are not NOPs or prefetches. This change also does the same for commitedOps. InstsCommitted from O3 commit.*, which tracks all instructions committed, has been removed. CommitCPUStats::numInsts replaces it in O3. The same has been done for opsCommitted. Because IPC and CPI calculations are handled in BaseCPU, removed IPC and CPI stats from O3 cpu.*. Change-Id: I9f122c9a9dafccd5342f18056f282f3dad8b1b1e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67393 Tested-by: kokoro <[email protected]> Reviewed-by: Bobby Bruce <[email protected]> Maintainer: Bobby Bruce <[email protected]>
The stats moved are from fetch.hh and fetch.cc of O3. Stat branches is now tracked by numBranches. Stat branchRate is now tracked by branchRate in FetchCPUStats. Stat rate is tracked by fetchRate. Stat insts is tracked by numInsts. Stat icacheStallCycles is tracked by icacheStallCycles in FetchCPUStats. Change-Id: I48313614edd078631df4ef6b00982c335798fcb1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67394 Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Bobby Bruce <[email protected]>
Moved numInsts, numBranches, numNop, numRefs, numLoadInsts, numRate to Base. Merged numRefs into numMemRefs of ExecuteCPUStats. Renamed numRate to instRate. Updated formatting in ExecuteCPUStats group. Change-Id: I1fd3a989d917eb2ffaa865b067b80e266d6f55bc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67395 Tested-by: kokoro <[email protected]> Reviewed-by: Bobby Bruce <[email protected]> Maintainer: Bobby Bruce <[email protected]>
Replaced committedInsts stats of KVM CPU with commitStats.numInsts of BaseCPU. This results in IPC and CPI printing in stats.txt for KVM simulations. Change-Id: I02395630fc50a69adebf11f4ed39d9cefb852e1f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67396 Reviewed-by: Andreas Sandberg <[email protected]> Maintainer: Andreas Sandberg <[email protected]> Tested-by: kokoro <[email protected]>
The lock feature will let M mode do memory permission check before R/W/X data. If the lock bit of pmpicfg set, then the pmpicfg and pmpaddri will ignore the update value later until CPU reset, and pmpaddri-1 will ignore if the TOR A field is set. The following is add in CL: 1. Add condition to run PMP check when any lock bit of pmp tables is set 2. Add PMP_LOCK bit check when try to update pmpaddr and pmpcfg 3. If there is no PMP entry matches and priviledge mode is M, no fault generated 4. If the address matches PMP entry, return no fault if priviledge mode is M and lock bit is not set For more details about PMP, please see RISC-V Spec Volumn II, Priviledge Archtecture, Ver 1.12, Section 3.7 Physical Memory Protection Change-Id: I3e7c5824d6c05f2ea928ee9ec7714f7271e4c58c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68057 Reviewed-by: Ayaz Akram <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Yu-hsin Wang <[email protected]> Maintainer: Bobby Bruce <[email protected]>
The weekly test script was implicitly assuming that no m5out directory existed in the folder where the script was run. However, if a prior test ran and failed, it would not clean up its m5out directory, causing the weekly tests to fail. This commit resolves this by removing the m5out directory before trying to run any tests in the weekly script. Moreover, we also update the weekly script to explicitly remove this m5out directory at the end of the script. Change-Id: If10c59034528e171cc2c5dacb928b3a81d6b8c50 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67198 Reviewed-by: Bobby Bruce <[email protected]> Maintainer: Bobby Bruce <[email protected]> Tested-by: kokoro <[email protected]>
These all look like valid (but harmless) diagnostics to me and are all simple to fix. Most of them can be fixed by using ASSERT_* variants of the GTest checkers to ensure that the remainder of the function is not executed and the uninitialized result isn't touched. Change-Id: Ib5fe2ac2ec539c880d670ebc3321ce98940c7e38 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68517 Tested-by: kokoro <[email protected]> Maintainer: Bobby Bruce <[email protected]> Reviewed-by: Bobby Bruce <[email protected]> Reviewed-by: Daniel Carvalho <[email protected]>
This reverts this relationchain: https://gem5-review.googlesource.com/c/public/gem5/+/67396/6 This was pre-maturely submitted before all testing and checking was done. To be safe this has been reverted. When all testing and checks are completed, this revert will be undone. Change-Id: I2a88cadfee03c1fc81932e6548938db108786dd2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68717 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Bobby Bruce <[email protected]> Reviewed-by: Bobby Bruce <[email protected]> Tested-by: kokoro <[email protected]>
We have a setup that requires manual startup of an ssh proxy to access license server, and without that, gem5 takes about a minute until the license checkout times out (until then, it's unclear why nothing is happening). We asked ARM for a way to decrease timeouts, but that doesn't seem to be easy to do. Change-Id: I37b84fd52cb7fb221a9e48dcb52a33a11f4d1580 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68177 Reviewed-by: Gabe Black <[email protected]> Maintainer: Gabe Black <[email protected]> Tested-by: kokoro <[email protected]>
Used the "power-hello" resource to make an stdlib example script for that resource Change-Id: Ia8a051330e263617aa0e2ef08321d01cfa1093c4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68737 Reviewed-by: Boris Shingarov <[email protected]> Maintainer: Boris Shingarov <[email protected]> Tested-by: kokoro <[email protected]>
We should be using gem5.components instead of python.gem5.components. In https://gem5-review.git.corp.google.com/c/public/gem5/+/68518 I was seeing the RISC-V tests fail with `ModuleNotFoundError: No module named 'python.gem5.components.processors.base_cpu_core'`. This fixes the issue for me with the RISC-V tests. I also searched for other similar imports and I've removed a similar (unused) one in x86_boot_exit_run.py. Change-Id: I61a0c4c27724854956f778f14e1fcfafea927ffd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68757 Reviewed-by: Bobby Bruce <[email protected]> Maintainer: Bobby Bruce <[email protected]> Tested-by: kokoro <[email protected]>
The CSRData map uses a RISC-V CSR number as the key rather than one of the MISCREG_* enumerators. Use MiscRegNames[] instead to stringify the argument for the debug message. Change-Id: I2533bc29d148d3b34c01022eeaeedf64c39a99b9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68759 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
Change-Id: I2d06c842955aa1868053a0d852fc523392480154 Signed-off-by: Hoa Nguyen <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68857 Tested-by: kokoro <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Jason Lowe-Power <[email protected]>
mem_mode is supposed to be atomic_noncaching when running AtomicSimpleCPU with Ruby cache. Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93 Signed-off-by: Hoa Nguyen <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68877 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
That header currently contains type traits that derive the class, the return type and the arguments of a member function from a pointer to that member function. Change-Id: I41dd41056f507016219d6111d25c8cb4c2ad3439 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67652 Reviewed-by: Daniel Carvalho <[email protected]> Maintainer: Daniel Carvalho <[email protected]> Tested-by: kokoro <[email protected]>
This new event class simplifies the use of EventWrapper and aims at superseeding it. EventWrapper has been redefined in terms of MemberEventWrapper. MemberEventWrapper makes use of the new type traits to simplify template parameterization and encourage its use over SimpleEvent that often wraps a lambda that merely calls a member function. Change-Id: Ie59e4c51705b9c2b2faa27097678d7d85f5b99c6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67653 Reviewed-by: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]> Maintainer: Daniel Carvalho <[email protected]> Reviewed-by: Daniel Carvalho <[email protected]>
This should return the number of standard features, not the number of extended features. Change-Id: Ieb3a36d832cee603f1efd39b4f430b5ac0478561 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70778 Maintainer: Matt Sinclair <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Matt Sinclair <[email protected]>
Add support for MI200-like device. This includes adding PCI IDs and new MMIOs for the device, a different MAP_PROCESS packet, and a different calculation for the number of VGPRs. Change-Id: I0fb7b3ad928826beaa5386d52a94ba504369cb0d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70317 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
Write queue drain logic seems off currently. An event is scheduled if the write queue is empty instead of non-empty. There is no check to see if draining is complete when bus is in write mode. Finally the power down check on drain always fails if DRAM powerdown is disabled. This changeset reverses the drain conditional for the write queue to schedule an event if the write queue is *not* empty and checks in the event processing method that the queues are all empty so that signalDrainDone can be called. Lastly the powerdown state is ignored if DRAM powerdown is disabled. Powerdown is disabled in the GPU_VIPER protocol by default. This changeset successfully drains and checkpoints a GPUFS simulation using GPU_VIPER protocol. Change-Id: I5459856a694c9054b28677049a06b99b9ad91bbb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69917 Tested-by: kokoro <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]>
Add support for the Arm SVE Floating Point Matrix Multiply-Accumulate (FMMLA) instruction. Both 32-bit element (single precision) and 64-bit element (double precision) encodings are implemented, but because the associated required instructions (LD1RO*, etc) have not yet been implemented, the SVE Feature ID register 0 (ID_AA64ZFR0_EL1) has only been updated to indicate 32-bit element support at this time. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Additional Contributors: Giacomo Travaglini Change-Id: If3547378ffa48527fe540767399bcc37a5dab524 Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70726 Reviewed-by: Andreas Sandberg <[email protected]> Maintainer: Andreas Sandberg <[email protected]> Maintainer: Giacomo Travaglini <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Giacomo Travaglini <[email protected]>
Add support for the Arm SVE Load-Broadcast Octaword (LD1RO{B,H,W,D})
instructions. These are similar to the Load-Broadcast
Quadword (LD1RQ{B,H,W,D}) instructions, but work on a 32-byte memory
segment rather than a 16-byte memory segment. Consequently, the LD1ROx
implementations build on the code for the LD1RQx implementations.
For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)
Change-Id: I98ee4f56c8099bf40c9034baa488d318ae57d3aa
Reviewed-by: Richard Cooper <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70727
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
Add support for the 128-bit element encodings of the TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2 instructions, required by the Armv8.2 SVE Double-precision floating-point Matrix Multiplication instructions (ARMv8.2-F64MM). For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Change-Id: I496576340c48410fedb2cf6fc7d1a02e219b3bd4 Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70728 Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Reviewed-by: Giacomo Travaglini <[email protected]> Maintainer: Andreas Sandberg <[email protected]>
Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares support for ARMv8.2-F64MM. This indicates that all pre-requisites for Armv8.2 SVE FP64 double-precision floating-point matrix multiplication instructions have been met. FMMLA, and LD1RO* instructions have been implemented, as well as the 128-bit element variants of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Additional Contributors: Giacomo Travaglini Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440 Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70729 Tested-by: kokoro <[email protected]> Reviewed-by: Giacomo Travaglini <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Maintainer: Andreas Sandberg <[email protected]> Maintainer: Giacomo Travaglini <[email protected]>
Add support for the Arm SVE Integer Matrix Multiply-Accumulate (SMMLA, USMMLA, UMMLA) instructions. Because the associated SUDOT and USDOT instructions have not yet been implemented, the SVE Feature ID register 0 (ID_AA64ZFR0_EL1) has not yet been updated to indicate support for SVE Int8 matrix multiplication instructions at this time. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Additional Contributors: Giacomo Travaglini Change-Id: Ia50e28fae03634cbe04b42a9900bab65a604817f Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70730 Maintainer: Andreas Sandberg <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]>
Re-factored the Arm instruction decoder to add placeholders for the SVE Integer mixed-sign DOT product instructions. This has involved moving some existing decode helper functions. Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218 Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70731 Reviewed-by: Andreas Sandberg <[email protected]> Maintainer: Andreas Sandberg <[email protected]> Tested-by: kokoro <[email protected]>
Add support for the SVE mixed sign dot product instructions (USDOT, SUDOT) required by the Armv8.2 SVE Int8 matrix multiplication extension (ARMv8.2-I8MM). For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Change-Id: I83841654cee74b940f967b3a37b99d87c01bd92c Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70732 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Tested-by: kokoro <[email protected]>
Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares support for ARMv8.2-I8MM. This indicates that all pre-requisites for Armv8.2 SVE Int8 matrix multiplication instructions have been met. SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Additional Contributors: Giacomo Travaglini Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4 Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70733 Maintainer: Giacomo Travaglini <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Giacomo Travaglini <[email protected]> Maintainer: Andreas Sandberg <[email protected]>
Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and I8MM extensions. Initial latencies have been set to be the same as SimdMultAcc and SimdFloatMultAcc respectively. Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70734 Maintainer: Andreas Sandberg <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Maintainer: Giacomo Travaglini <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Giacomo Travaglini <[email protected]>
These lines break the current gem5 coding guidelines. Change-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70735 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Maintainer: Andreas Sandberg <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Tested-by: kokoro <[email protected]>
Add support for the Armv8.2-DotProd NEON extension. This provides the SDOT and UDOT SIMD Dot Product instructions. For more information please refer to the Arm Architecture Reference Manual (https://developer.arm.com/documentation/ddi0487/latest/). Change-Id: I4caa3b97a74c65f32421487c55c3e36427194e61 Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70736 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Maintainer: Andreas Sandberg <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
Add support for the Armv8.2-I8MM NEON extension. This provides the SUDOT and USDOT mixed-sign SIMD Dot Product instructions, as well as the SMMLA, UMMLA, and USMMLA SIMD Matrix Multiply-Accumulate instructions. For more information please refer to the Arm Architecture Reference Manual (https://developer.arm.com/documentation/ddi0487/latest/). Additional Contributors: Giacomo Travaglini Change-Id: I6fb9318f67cc9d2737079283e1a095630c4d2ad9 Reviewed-by: Richard Cooper <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70737 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Andreas Sandberg <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Andreas Sandberg <[email protected]> Tested-by: kokoro <[email protected]>
This extension is optional in Armv8.2 but mandatory since Armv8.5 We only implement this for AArch64 Change-Id: I063642ac24d27f0a81ba79b1d38f72468bb130eb Signed-off-by: Giacomo Travaglini <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70938 Reviewed-by: Richard Cooper <[email protected]> Tested-by: kokoro <[email protected]> Maintainer: Jason Lowe-Power <[email protected]>
This is just making the HCRX_EL2 register read/writable; trapping behaviour will be implemented with further extensions Change-Id: Id1ec42a754b7d999782edde3a8ec6c6099e3331e Signed-off-by: Giacomo Travaglini <[email protected]> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70939 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Richard Cooper <[email protected]> Tested-by: kokoro <[email protected]>
This patch changes the RISCVMatched Cache Hierarchy to
private L1 shared L2.
It also changes the RISCVMatched Core's parameters to
better match hardware performance.
Also, sizes are changed to MiB or KiB instead of MB
or KB, to match the datasheet.
All the changes that deviate from the datasheet and the
ARM HPI CPU (reference for pipeline parameters)
are documented.
The core parameters that are changed are:
- threadPolicy:
This is initialized to "SingleThreaded".
- decodeToExecuteForwardDelay:
This is changed from 1 to 2 to avoid a PMC address fault.
- fetch1ToFetch2BackwardDelay:
This is changed from 1 to 0 to better match hardware performance.
- fetch2InputBufferSize:
This is changed from 2 to 1 to better match hardware performance.
- decodeInputBufferSize:
This is changed from 3 to 2 to better match hardware performance.
- decodeToExecuteForwardDelay:
This is changed from 2 to 1 to better match hardware performance.
- executeInputBufferSize:
This is changed from 7 to 4 to better match hardware performance.
- executeMaxAccessesInMemory:
This is changed from 2 to 1 to better match hardware performance.
- executeLSQStoreBufferSize:
This is changed from 5 to 3 to better match hardware performance.
- executeBranchDelay:
This is changed from 1 to 2 to better match hardware performance.
- enableIdling:
This is changed to False to better match hardware performance.
- MemReadFU: changed to 2 cycles from 3 cycles.
The changes in the branch predictor are:
- BTBEntries:
This is changed from 16 entries to 32 entries.
- RASSize:
This is changed from 6 entries to 12 entries.
- IndirectSets:
This is changed from 8 sets to 16 sets.
- localPredictorSize:
This is changed from 8192 to 16384.
- globalPredictorSize:
This is changed from 8192 to 16384.
- choicePredictorSize:
This is changed from 8192 to 16384.
- localCtrBits:
This is changed from 2 to 4.
- globalCtrBits:
This is changed from 2 to 4.
- choiceCtrBits:
This is changed from 2 to 4.
Change-Id: I4235140f33be6a3b529a819ae6a7223cb88bb7ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70798
Maintainer: Bobby Bruce <[email protected]>
Tested-by: kokoro <[email protected]>
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
This change adds a single DDR5 memory inteface. A DDR5 DIMM contains two physical channels. Therefore, two instances of this interface should be used to model a DDR5 DIMM. The configuration includes 3 different speed bins models. The configuration is tested with different types of memory traffic using the traffic generator and shows performance similar to what is observed in existing literature [1]. One of the key features of DDR5 "same bank refresh" is yet not supported in gem5, but is expected to improve the performance of the DDR5 model. [1] Exploration of DDR5 with the Open-Source Simulator DRAMSys. Change-Id: I5856a10c8dcd92dbecc7fd4dcea0f674b2412dd7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68257 Maintainer: Jason Lowe-Power <[email protected]> Reviewed-by: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
This change adds a link to the common errors page that outputs whenever a fatal signal is raised, showing when the program aborts or segfaults. Change-Id: I88420a594423570af670b460cfce7c03c4208120 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70978 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Daniel Carvalho <[email protected]> Tested-by: kokoro <[email protected]> Reviewed-by: Daniel Carvalho <[email protected]>
This change updates the HBMCtrl such that both pseudo channels can be in separate states (read or write) at the same time. In addition, the controller queues are now always split in two halves for both pseudo channels. Change-Id: Ifb599e611ad99f6c511baaf245bad2b5c9210a86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65491 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
We have some customized protocols in gem5 repository and they require the include path from src directory. It causes the users of those protocols need to handle the include path correctly by theirselve. This is tedious and unstable. We should add the default include path in SIMGEN command line to prevent issues. Change-Id: I2a3748646567635d131a8fb4099e02e332691e97 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71118 Reviewed-by: Wei-Han Chen <[email protected]> Tested-by: kokoro <[email protected]> Maintainer: Jason Lowe-Power <[email protected]>
There is no GPU device in SE mode to get version from and no GPU driver in FS mode to get version from, so a conditional needs to be added depending on the mode to get the gfx version. Change-Id: I33fdafb60d351ebc5148e2248244537fb5bebd31 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71078 Tested-by: kokoro <[email protected]> Maintainer: Matt Sinclair <[email protected]> Reviewed-by: Matt Sinclair <[email protected]>
There are three bugs fixed in this patch: 1. The `dram_3_dir` was missing the "dramsim3" directory. 2. Missing `not` when checking if configs is a directory. 3. Missing `not` when checking if input file is a file. Change-Id: I185f4832c1c2f1ecc4e138c148ad7969ef9b6fd4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71038 Reviewed-by: Jason Lowe-Power <[email protected]> Maintainer: Jason Lowe-Power <[email protected]> Tested-by: kokoro <[email protected]>
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