Dram Cache Controller (Hit (rd/wr)+ Miss (rd)) #4

mbabaie · 2021-10-04T18:29:24Z

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Change-Id: Iacad811fb48cf65be8cfadab7fdb421ad0c98a6b

Change-Id: I3b782f6d72ef64a96d7a2d3133b745dc99d7a025

Change-Id: If38a31c4ba0af68d7b90a8cb2ee99a364b66d561

Change-Id: Ifbfbf4aff79cbab758a35ec2ba07c19fb0b99d43

Change-Id: I3d335f8c64a605c24c0136c06087e41779e5ea30

Change-Id: Ic50fab42b25fcd98d32fab5d849e896882f82d02

Change-Id: If79e442f3c562ab0455f1c35146a032524d4ec9b

Signed-off-by: Jason Lowe-Power <[email protected]>

Change-Id: Ie7f78f53c5a20b42ff73c1459aaff551a9de1705

Change-Id: Iea35abd1d85d22731b6859940517642420411452

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Change-Id: I888dcda7b7dbbaee6e39dce66245a2913b48817d

Change-Id: Ib1cc88d8daab2a896b848d41ff622a0f4ea99d1f

Change-Id: Id7a9742a140d9bd8de7f01326ce0181129d902de

Change-Id: I25f6dcc7bbf5b3057709633c4a8899aa518dbaf9

Change-Id: I611cf06579ecb47e239d3b43163764f0e3a4abeb

powerjg

I don't think it's feasible for me to review the dcache_ctrl and dcmem_interface as there's no way for me to tell what's new vs. what came from the original file. We need to do something to reduce the code duplication between the DRAM models and the DRAM cache models before a review is feasible.

Below are a few comments. Make sure you put copyrights in all files that you create/modify.

powerjg · 2021-10-05T15:47:00Z

.vscode/settings.json

@@ -0,0 +1,75 @@
+{


This file shouldn't be committed.

I strongly suggest creating a PR like this, then looking at it yourself and doing a "self review" to fix some of these low hanging fruits

powerjg · 2021-10-05T15:48:31Z

simple.py

+system.generator.port = system.mem_ctrl.port
+
+def createRandomTraffic(tgen):
+    yield tgen.createRandom(100000000000,   # duration


I know you're changing this a lot. I would suggest making this an argument to the script with optparse

powerjg · 2021-10-05T15:49:22Z

simple.py

+m5.instantiate()
+system.generator.start(createRandomTraffic(system.generator))
+#system.generator.start(createLinearTraffic(system.generator))
+exit_event = m5.simulate()


This needs a newline at the end of the file. You should configure your editor to automatically add newlines at the end of the file and remove all trailing whitespace.

powerjg · 2021-10-05T15:49:40Z

simple.py

+system.generator.start(createRandomTraffic(system.generator))
+#system.generator.start(createLinearTraffic(system.generator))


This should be an option, too.

Whatever things in this script that you want to change frequently should be command line options. That's the purpose of command line options :)

powerjg · 2021-10-05T15:50:34Z

src/mem/DCMemInterface.py

@@ -0,0 +1,66 @@
+from m5.params import *


Needs a copyright.

powerjg · 2021-10-05T15:53:55Z

src/mem/DcacheCtrl.py

+    # JASON: let's get this size from the interface
+    dram_cache_size = Param.MemorySize('1024MiB', "DRAM cache size")


Don't forget this

powerjg · 2021-10-05T15:54:14Z

src/mem/DcacheCtrl.py

+    dram = Param.DRAMDCInterface(NULL, "DRAM interface")
+
+    # Interface to non-volatile media
+    nvm = Param.NVMDCInterface(NULL, "NVM interface")


I believe both of these are required. They shouldn't default to NULL

powerjg · 2021-10-05T15:55:06Z

src/mem/HetMemCtrl.py

@@ -0,0 +1,59 @@
+#Copyright (c) 2021 The Regents of the University of California.


What is this file? What is DcacheCtrl? Which one are you using?

powerjg · 2021-10-05T15:55:21Z

src/mem/NVMDCInterface.py

@@ -0,0 +1,69 @@
+


Must have copyright

powerjg · 2021-10-05T15:56:34Z

src/mem/packet.hh

@@ -350,6 +350,8 @@ class Packet : public Printable
    */
    PacketDataPtr data;

+    PacketDataPtr cacheLineRead;


Why are these changes needed? It would be best if packet doesn't need to be changed.

Change-Id: I335c790c560a023353981f19f119b6adcb2b18ef

Change-Id: I331ee5f0cffe109f2a766a7f0052dd9614bd1c01

aakahlow and others added 21 commits February 23, 2021 23:03

mem: [wip] a rough sketch of integrated mem controller

1f6ff60

Change-Id: Iacad811fb48cf65be8cfadab7fdb421ad0c98a6b

init files

63af958

added Qs

e982073

mem: not unified interface, dcache ctrl always hit dram cache

4c327c5

Change-Id: I3b782f6d72ef64a96d7a2d3133b745dc99d7a025

mem: not unified interface, dcache ctrl always hit dram cache

d067acf

Change-Id: If38a31c4ba0af68d7b90a8cb2ee99a364b66d561

mem: everything before unifying ctrl and intrfc

ae70805

mem: more fix and updates

a0cad47

Change-Id: Ifbfbf4aff79cbab758a35ec2ba07c19fb0b99d43

mem: more fix and updates

0a903ab

Change-Id: I3d335f8c64a605c24c0136c06087e41779e5ea30

mem: minor fix

6b016e7

Change-Id: Ic50fab42b25fcd98d32fab5d849e896882f82d02

mem: minor fix

d7db7b9

Change-Id: If79e442f3c562ab0455f1c35146a032524d4ec9b

mem: Comments on dram cache controller

14253ff

Signed-off-by: Jason Lowe-Power <[email protected]>

mem: more updates

56e1ad6

Change-Id: Ie7f78f53c5a20b42ff73c1459aaff551a9de1705

mem: more update

e2d5658

Change-Id: Iea35abd1d85d22731b6859940517642420411452

mem: more update for hit only

cfced46

Change-Id: I724a84be596e84327488f485ded727f69e60ced2

mem: more update

1de8cf2

Change-Id: I7812f21e19552aab60e003d57ae1b76fc1bf6769

mem: pull from shasta

805664c

Change-Id: I56d5178272a10f1d811de721c4c19962f4fd2abb

mem: adding responses for hits

b39a4ff

Change-Id: I4bea6ea7b61ad7ca404016e6f584c7a6be61b1f0

mem: adding event handler for initial reads

0979c8d

Change-Id: I888dcda7b7dbbaee6e39dce66245a2913b48817d

mem: more updates

d5256bd

Change-Id: Ib1cc88d8daab2a896b848d41ff622a0f4ea99d1f

mem: fixed the assert failed in the memInterface

cc5f320

Change-Id: Id7a9742a140d9bd8de7f01326ce0181129d902de

mem: added Read Miss Clean cases

5d1bacc

Change-Id: I25f6dcc7bbf5b3057709633c4a8899aa518dbaf9

mbabaie changed the title ~~Hit Only Dram Cache Controller~~ Dram Cache Controller (Hit (rd/wr)+ Miss (rd)) Oct 5, 2021

mem: more updates

e8f3bd7

Change-Id: I611cf06579ecb47e239d3b43163764f0e3a4abeb

powerjg reviewed Oct 5, 2021

View reviewed changes

mbabaie added 2 commits October 6, 2021 17:24

mem: all the cases implemented and debugged

8c549d0

Change-Id: I335c790c560a023353981f19f119b6adcb2b18ef

mem: mem: all the cases implemented and debugged

69c6d01

Change-Id: I331ee5f0cffe109f2a766a7f0052dd9614bd1c01

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Dram Cache Controller (Hit (rd/wr)+ Miss (rd)) #4

Dram Cache Controller (Hit (rd/wr)+ Miss (rd)) #4

mbabaie commented Oct 4, 2021

powerjg left a comment

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

powerjg Oct 5, 2021

		system.generator.start(createRandomTraffic(system.generator))
		#system.generator.start(createLinearTraffic(system.generator))

		# JASON: let's get this size from the interface
		dram_cache_size = Param.MemorySize('1024MiB', "DRAM cache size")

		@@ -0,0 +1,59 @@
		#Copyright (c) 2021 The Regents of the University of California.

Dram Cache Controller (Hit (rd/wr)+ Miss (rd)) #4

Are you sure you want to change the base?

Dram Cache Controller (Hit (rd/wr)+ Miss (rd)) #4

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mbabaie commented Oct 4, 2021

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