Merge pull request #27 from darchr/set_associative

Merging the changes for tag probing in TDRAM to the main branch (set_associative)

src/cpu/testers/dr_trace_player/trace_player.cc

@@ -86,6 +86,7 @@ DRTracePlayer::tryExecuteInst(DRTraceReader::TraceRef &cur_ref)
         // End of trace for this player exit the simulation
         // TODO: Move this to when the last instruction is completed
         exitSimLoopNow("End of DRTrace");
+        return;
     }
 
     DPRINTF(DRTrace, "Exec reference pc: %0#x, addr: %0#x, size: %d, "

src/cpu/testers/dr_trace_player/trace_reader.cc

@@ -171,6 +171,10 @@ DRTraceReader::getNextTraceReference(unsigned player_id)
         case TRACE_TYPE_PREFETCHT1:
         case TRACE_TYPE_PREFETCHT2:
         case TRACE_TYPE_PREFETCHNTA:
+            if (raw_entry.addr == 0) {
+                warn("Encountered a prefetch req with Addr = 0 \n");
+                return getNextTraceReference(player_id);
+	     }
             ref.addr = raw_entry.addr;
             ref.size = raw_entry.size;
             ref.isValid = true;

src/mem/DRAMInterface.py

@@ -187,13 +187,13 @@ class DRAMInterface(MemInterface):
     tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
 
     tTAGBURST = Param.Latency("0ns", "tRL_FAST")
-    tRL_FAST   = Param.Latency("0ns", "tRL_FAST")
+    tRLFAST   = Param.Latency("0ns", "tRL_FAST")
     tHM2DQ    = Param.Latency("0ns", "tHM2DQ")
     tRTW_int  = Param.Latency("0ns", "tRTW_int")
     tRFBD     = Param.Latency("0ns", "tRFBD")
     tRCD_FAST = Param.Latency("0ns", "tRCD_FAST")
-    tRC_FAST  = Param.Latency("0ns", "tRCD_FAST")
     flushBuffer_high_thresh_perc = Param.Percent(0, "Threshold to force writes")
+    flush_buffer_size = Param.Unsigned(0, "flush buffer size")
 
     # number of data beats per clock. with DDR, default is 2, one per edge
     # used in drampower.cc
@@ -1304,12 +1304,11 @@ class TDRAM(DRAMInterface):
 
     # new
     tTAGBURST = "1ns"
-    tRL_FAST = "1ns"
+    tRLFAST = "1ns"
     tHM2DQ = "1ns"
     tRTW_int = "2ns"
     tRFBD = "2ns"
     tRCD_FAST = "7.5ns"
-    tRC_FAST = "10.5ns"
     enable_read_flush_buffer = True
     flushBuffer_high_thresh_perc = 80
 
@@ -1391,13 +1390,14 @@ class TDRAM_32(DRAMInterface):
 
     # new
     tTAGBURST = "0.5ns"
-    tRL_FAST = "7.5ns"
+    tRLFAST = "7.5ns"
     tHM2DQ = "0ns"
     tRTW_int = "1ns"
     tRFBD = "1ns"
     tRCD_FAST = "7.5ns"
     enable_read_flush_buffer = True
     flushBuffer_high_thresh_perc = 80
+    flush_buffer_size = 32
 
     tRP = "14ns"
 

src/mem/PolicyManager.py

@@ -5,7 +5,7 @@
 from m5.objects.AbstractMemory import AbstractMemory
 from m5.objects.DRAMInterface import *
 
-class Policy(Enum): vals = ['CascadeLakeNoPartWrs', 'Oracle', 'BearWriteOpt', 'Rambus', 'RambusTagProbOpt']
+class Policy(Enum): vals = ['CascadeLakeNoPartWrs', 'Oracle', 'BearWriteOpt', 'Rambus']
 class ReplPolicySetAssoc(Enum): vals = ['bip_rp', 'brrip_rp', 'dueling_rp', 'fifo_rp', 'lfu_rp', 'lru_rp', 'mru_rp', 'random_rp', 'second_chance_rp', 'ship_rp', 'tree_plru_rp', 'weighted_lru_rp']
 
 class PolicyManager(AbstractMemory):

src/mem/abstract_mem.hh

@@ -46,7 +46,6 @@
 #ifndef __MEM_ABSTRACT_MEMORY_HH__
 #define __MEM_ABSTRACT_MEMORY_HH__
 
-#include "enums/Policy.hh"
 #include "mem/backdoor.hh"
 #include "mem/port.hh"
 #include "params/AbstractMemory.hh"
@@ -226,8 +225,6 @@ class AbstractMemory : public ClockedObject
 
     void initState() override;
 
-    enums::Policy locMemPolicy;
-
     virtual Tick get_tRP() { panic("AbstractMemory get_tRP should not be executed from here.\n");
                              return false;}
     virtual Tick get_tRCD_RD() { panic("AbstractMemory get_tRCD_RD should not be executed from here.\n");

src/mem/dram_interface.cc

@@ -48,7 +48,6 @@
 #include "debug/DRAMPower.hh"
 #include "debug/DRAMState.hh"
 #include "debug/MemCtrl.hh"
-#include "enums/Policy.hh"
 #include "sim/system.hh"
 
 namespace gem5
@@ -455,16 +454,13 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
     // update the packet ready time
     Tick stall_delay = 0;
     if(mem_pkt->isTagCheck) {
-
         assert(mem_pkt->isLocMem);
-        
+
         // Calculating the tag check ready time
         if (mem_pkt->pkt->owIsRead) {
-            assert((cmd_at + tRCD_FAST + tRL_FAST) > tRCD_RD);
-            mem_pkt->tagCheckReady = (cmd_at + tRCD_FAST + tRL_FAST) - tRCD_RD;
+            mem_pkt->tagCheckReady = cmd_at - tRCD_RD + tRCD_FAST + tRLFAST;
         } else {
-            assert((cmd_at + tRCD_FAST + tRL_FAST) > (tRCD_RD + tRTW_int));
-            mem_pkt->tagCheckReady = (cmd_at + tRCD_FAST + tRL_FAST) - (tRCD_RD + tRTW_int);
+            mem_pkt->tagCheckReady = cmd_at - tRCD_RD - tRTW_int + tRCD_FAST + tRLFAST;
         }
         stats.tagResBursts++;
 
@@ -482,7 +478,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         // Calculating the data ready time
         if (mem_pkt->pkt->owIsRead) {
 
-            mem_pkt->readyTime = cmd_at + std::max(tRL,  tRL_FAST + tHM2DQ) + tBURST;
+            mem_pkt->readyTime = cmd_at + std::max(tRL, tRLFAST + tHM2DQ) + tBURST;
 
             // Rd Miss Clean
             if (mem_pkt->pkt->owIsRead && !mem_pkt->pkt->isHit && !mem_pkt->pkt->isDirty) {
@@ -570,7 +566,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
 
                 tempFlushBuffer.push_back(std::make_pair(pushBackFBTick, mem_pkt->pkt->dirtyLineAddr));
 
-                if ((tempFlushBuffer.size() + flushBuffer.size()) >= (banksPerRank * flushBufferHighThreshold) &&
+                if ((tempFlushBuffer.size() + flushBuffer.size()) >= (flushBufferSize * flushBufferHighThreshold) &&
                      !readFlushBufferEvent.scheduled() &&
                      !flushBuffer.empty()) {
 
@@ -655,7 +651,6 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         }
     }
 
-
     DPRINTF(DRAMT, "curr pkt, addr: %d, isRd: %d, isTC: %d, bank %d, row %d, act: %d, RdAlw: %d, WrAlw: %d, cmd: %d, rdy: %d\n", 
     mem_pkt->getAddr(), mem_pkt->isRead(), mem_pkt->isTagCheck, (unsigned) mem_pkt->bank, (unsigned) mem_pkt->row,
     act_at/1000, bank_ref.rdAllowedAt/1000, bank_ref.wrAllowedAt/1000, cmd_at/1000, mem_pkt->readyTime/1000);
@@ -897,10 +892,10 @@ DRAMInterface::DRAMInterface(const DRAMInterfaceParams &_p)
       tRFC(_p.tRFC), tREFI(_p.tREFI), tRRD(_p.tRRD), tRRD_L(_p.tRRD_L),
       tPPD(_p.tPPD), tAAD(_p.tAAD),
       tXAW(_p.tXAW), tXP(_p.tXP), tXS(_p.tXS),
-      tTAGBURST(_p.tTAGBURST),  tRL_FAST(_p. tRL_FAST), tHM2DQ(_p.tHM2DQ),
+      tTAGBURST(_p.tTAGBURST), tRLFAST(_p.tRLFAST), tHM2DQ(_p.tHM2DQ),
       tRTW_int(_p.tRTW_int), tRFBD(_p.tRFBD), tRCD_FAST(_p.tRCD_FAST),
-      tRC_FAST(_p.tRC_FAST),
       flushBufferHighThreshold(_p.flushBuffer_high_thresh_perc / 100.0),
+      flushBufferSize(_p.flush_buffer_size),
       clkResyncDelay(_p.tBURST_MAX),
       dataClockSync(_p.data_clock_sync),
       burstInterleave(tBURST != tBURST_MIN),
@@ -2283,8 +2278,6 @@ DRAMInterface::DRAMStats::DRAMStats(DRAMInterface &_dram)
              "Maximum flush buffer length when enqueuing"),
     ADD_STAT(refSchdRFB, statistics::units::Count::get(),
              "Maximum flush buffer length when enqueuing"),
-    ADD_STAT( actDelayedDueToTagAct, statistics::units::Count::get(),
-             " "),
     ADD_STAT(perBankRdBursts, statistics::units::Count::get(),
              "Per bank write bursts"),
     ADD_STAT(perBankWrBursts, statistics::units::Count::get(),

src/mem/dram_interface.hh

@@ -509,13 +509,13 @@ class DRAMInterface : public MemInterface
     const Tick tXP;
     const Tick tXS;
     const Tick tTAGBURST;
-    const Tick tRL_FAST;
+    const Tick tRLFAST;
     const Tick tHM2DQ;
     const Tick tRTW_int;
     const Tick tRFBD;
     const Tick tRCD_FAST;
-    const Tick tRC_FAST;
     float flushBufferHighThreshold;
+    unsigned flushBufferSize;
     const Tick clkResyncDelay;
     const bool dataClockSync;
     const bool burstInterleave;
@@ -602,7 +602,6 @@ class DRAMInterface : public MemInterface
         statistics::Scalar totPktsPushedFB;
         statistics::Scalar maxFBLenEnq;
         statistics::Scalar refSchdRFB;
-        statistics::Scalar actDelayedDueToTagAct;
 
         /** DRAM per bank stats */
         statistics::Vector perBankRdBursts;
@@ -872,7 +871,7 @@ class DRAMInterface : public MemInterface
     Tick getTRCDFAST() override { return tRCD_FAST;}
 
     void updateTagActAllowed(unsigned rankNumber, unsigned bankNumber, Tick BSlotTagBankBusyAt) override;
-    
+
     DRAMInterface(const DRAMInterfaceParams &_p);
 };
 

src/mem/mem_ctrl.cc

@@ -264,7 +264,6 @@ MemCtrl::addToReadQueue(PacketPtr pkt,
             mem_pkt = mem_intr->decodePacket(pkt, addr, size, true,
                                                     mem_intr->pseudoChannel);
             mem_pkt->isTagCheck = pkt->isTagCheck;
-            mem_pkt->isLocMem = pkt->isLocMem;
 
             // Increment read entries of the rank (dram)
             // Increment count to trigger issue of non-deterministic read (nvm)
@@ -345,7 +344,6 @@ MemCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pkt_count,
             mem_pkt = mem_intr->decodePacket(pkt, addr, size, false,
                                                     mem_intr->pseudoChannel);
             mem_pkt->isTagCheck = pkt->isTagCheck;
-            mem_pkt->isLocMem = pkt->isLocMem;
 
             // Default readyTime to Max if nvm interface;
             //will be reset once read is issued
@@ -715,7 +713,6 @@ MemCtrl::sendTagCheckRespond(MemPacket* mem_pkt)
     PacketPtr tagCheckResPkt = getPacket(mem_pkt->addr, 8, MemCmd::ReadReq);
 
     tagCheckResPkt->isTagCheck = mem_pkt->pkt->isTagCheck;
-    tagCheckResPkt->isLocMem = mem_pkt->pkt->isLocMem;
     tagCheckResPkt->owIsRead = mem_pkt->pkt->owIsRead;
     tagCheckResPkt->isHit = mem_pkt->pkt->isHit;
     tagCheckResPkt->isDirty = mem_pkt->pkt->isDirty;
@@ -937,7 +934,6 @@ MemCtrl::doBurstAccess(MemPacket* mem_pkt, MemInterface* mem_intr)
     // conservative estimate of when we have to schedule the next
     // request to not introduce any unecessary bubbles. In most cases
     // we will wake up sooner than we have to.
-    assert(mem_intr->nextBurstAt > mem_intr->commandOffset());
     mem_intr->nextReqTime = mem_intr->nextBurstAt - mem_intr->commandOffset();
 
     // Update the common bus stats
@@ -1524,8 +1520,6 @@ MemCtrl::handleTCforBSlotPkt(MemPacketQueue::iterator BslotPktIt, Tick BSlotTagB
 
         return;
     }
-
-
 }
 
 MemCtrl::CtrlStats::CtrlStats(MemCtrl &_ctrl)
@@ -1574,17 +1568,6 @@ MemCtrl::CtrlStats::CtrlStats(MemCtrl &_ctrl)
              "Reads before turning the bus around for writes"),
     ADD_STAT(wrPerTurnAround, statistics::units::Count::get(),
              "Writes before turning the bus around for reads"),
-
-    ADD_STAT(noCandidBSlot, statistics::units::Count::get(),
-             " "),
-    ADD_STAT(foundCandidBSlot, statistics::units::Count::get(),
-             " "),
-    ADD_STAT(foundCandidBSlotRH, statistics::units::Count::get(),
-             " "),
-    ADD_STAT(foundCandidBSlotRMC, statistics::units::Count::get(),
-             " "),
-    ADD_STAT(foundCandidBSlotRMD, statistics::units::Count::get(),
-             " "),
 
     ADD_STAT(bytesReadWrQ, statistics::units::Byte::get(),
              "Total number of bytes read from write queue"),

src/mem/mem_ctrl.hh

@@ -170,7 +170,6 @@ class MemPacket
     bool probedRdMD = false;
 
 
-
     /**
      * Set the packet QoS value
      * (interface compatibility with Packet)
@@ -635,12 +634,6 @@ class MemCtrl : public qos::MemCtrl
         statistics::Histogram rdPerTurnAround;
         statistics::Histogram wrPerTurnAround;
 
-        statistics::Scalar noCandidBSlot;
-        statistics::Scalar foundCandidBSlot;
-        statistics::Scalar foundCandidBSlotRH;
-        statistics::Scalar foundCandidBSlotRMC;
-        statistics::Scalar foundCandidBSlotRMD;
-
         statistics::Scalar bytesReadWrQ;
         statistics::Scalar bytesReadSys;
         statistics::Scalar bytesWrittenSys;

src/mem/mem_interface.hh

@@ -97,14 +97,13 @@ class MemInterface : public AbstractMemory
         Tick wrAllowedAt;
         Tick preAllowedAt;
         Tick actAllowedAt;
-        Tick tagActAllowedAt;
 
         uint32_t rowAccesses;
         uint32_t bytesAccessed;
 
         Bank() :
             openRow(NO_ROW), bank(0), bankgr(0),
-            rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0), tagActAllowedAt(0),
+            rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
             rowAccesses(0), bytesAccessed(0)
         { }
     };
@@ -424,7 +423,6 @@ class MemInterface : public AbstractMemory
 
     virtual void updateTagActAllowed(unsigned rankNumber, unsigned bankNumber, Tick BSlotTagAllowedAt)
         { panic("MemInterface updateTagActAllowed should not be executed from here.\n"); }
-
 
     typedef MemInterfaceParams Params;
     MemInterface(const Params &_p);

src/mem/packet.hh

@@ -298,7 +298,6 @@ class Packet : public Printable, public Extensible<Packet>
     typedef gem5::Flags<FlagsType> Flags;
 
     bool isTagCheck = false;
-    bool isLocMem = false;
     bool owIsRead = false;
     bool isHit = false;
     bool isDirty = false;

src/mem/policy_manager.cc

@@ -20,7 +20,7 @@ PolicyManager::PolicyManager(const PolicyManagerParams &p):
     farReqPort(name() + ".far_req_port", *this),
     locBurstSize(p.loc_burst_size),
     farBurstSize(p.far_burst_size),
-    // locMemPolicy(p.loc_mem_policy),
+    locMemPolicy(p.loc_mem_policy),
     locMem(p.loc_mem),
     replacementPolicy(p.replacement_policy),
     dramCacheSize(p.dram_cache_size),
@@ -143,19 +143,6 @@ PolicyManager::findInORB(Addr addr)
     return found;
 }
 
-unsigned
-PolicyManager::findDupInORB(Addr addr)
-{
-    unsigned count=0;
-    for (const auto& e : ORB) {
-        if (e.second->owPkt->getAddr() == addr) {
-
-           count++;
-        }
-    }
-    return count;
-}
-
 void
 PolicyManager::init()
 {
@@ -435,6 +422,7 @@ PolicyManager::processTagCheckEvent()
     auto orbEntry = ORB.at(pktTagCheck.front());
     assert(orbEntry->pol == enums::Rambus || orbEntry->pol == enums::RambusTagProbOpt);
     assert(orbEntry->validEntry);
+    findInORB(orbEntry->owPkt->getAddr());
     assert(orbEntry->state == tagCheck);
     assert(!orbEntry->issued);
 
@@ -452,7 +440,6 @@ PolicyManager::processTagCheckEvent()
     }
 
     tagCheckPktPtr->isTagCheck = true;
-    tagCheckPktPtr->isLocMem = true;
     tagCheckPktPtr->owIsRead = orbEntry->owPkt->isRead();
     tagCheckPktPtr->isHit = orbEntry->isHit;
     tagCheckPktPtr->isDirty = orbEntry->prevDirty;
@@ -506,7 +493,7 @@ PolicyManager::processLocMemReadEvent()
     PacketPtr rdLocMemPkt = getPacket(pktLocMemRead.front(),
                                    blockSize,
                                    MemCmd::ReadReq);
-    rdLocMemPkt->isLocMem = true;
+
     if (locReqPort.sendTimingReq(rdLocMemPkt)) {
         DPRINTF(PolicyManager, "loc mem read is sent : %lld--> %d, %d, %d, %d, %d, %d\n", rdLocMemPkt->getAddr(), ORB.size(), pktLocMemRead.size(),
         pktLocMemWrite.size(), pktFarMemRead.size(), pktFarMemWrite.size(), CRB.size());
@@ -541,7 +528,6 @@ PolicyManager::processLocMemWriteEvent()
     PacketPtr wrLocMemPkt = getPacket(pktLocMemWrite.front(),
                                    blockSize,
                                    MemCmd::WriteReq);
-    wrLocMemPkt->isLocMem = true;
     assert(!wrLocMemPkt->isTagCheck);
 
     if (locReqPort.sendTimingReq(wrLocMemPkt)) {
@@ -2356,12 +2342,14 @@ PolicyManager::checkConflictInORB(PacketPtr pkt)
             sameIndex.push_back(e->first);
         }
     }
+
     if (sameIndex.size() == assoc) {
         for (int i=0; i<assoc; i++) {
             ORB.at(sameIndex.at(i))->conflict = true;
         }
         return true;
     }
+
     return false;
 }
 
@@ -3328,6 +3316,7 @@ PolicyManager::unserialize(CheckpointIn &cp)
             }
         }
     }
+    //std::cout << "Counters: " << num_entries << " , " << countInvalid << " , " << countValid << "\n";
 }
 
 int