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darchr · Jul 31, 2023 · 7bef9f3 · 7bef9f3
1 parent 9751ba3
commit 7bef9f3
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Showing 6 changed files with 1,694 additions and 762 deletions.
diff --git a/configs-npb-gapbs/restore_both.py b/configs-npb-gapbs/restore_both.py
@@ -146,11 +146,6 @@ def parse_options():
         type=int,
         help="bypass DRAM cache",
     )
-    parser.add_argument(
-        "flushBufferSize",
-        type=int,
-        help="flush buffer size",
-    )
     parser.add_argument("--do_analysis", action="store_true", default=False)
     return parser.parse_args()
 
@@ -267,7 +262,6 @@ def run():
         args.is_link,
         args.link_lat,
         args.bypass,
-        args.flushBufferSize,
         args,
         restore=True,
     )

diff --git a/configs-npb-gapbs/system/ruby_system_new.py b/configs-npb-gapbs/system/ruby_system_new.py
@@ -34,7 +34,7 @@
 
 class MyRubySystem(System):
 
-    def __init__(self, kernel, disk, mem_sys, num_cpus, assoc, dcache_size, main_mem_size, policy, is_link, link_lat, bypass, flushBufferSize, opts, restore=False):
+    def __init__(self, kernel, disk, mem_sys, num_cpus, assoc, dcache_size, main_mem_size, policy, is_link, link_lat, bypass, opts, restore=False):
         super(MyRubySystem, self).__init__()
         print("Creating MyRubySystem")
         self._opts = opts
@@ -72,7 +72,7 @@ def __init__(self, kernel, disk, mem_sys, num_cpus, assoc, dcache_size, main_mem
         self.createCPU(num_cpus)
 
         # self.intrctrl = IntrControl()
-        self._createMemoryControllers(assoc, dcache_size, policy, is_link, link_lat, bypass, flushBufferSize)
+        self._createMemoryControllers(assoc, dcache_size, policy, is_link, link_lat, bypass)
 
         # Create the cache hierarchy for the system.
         if mem_sys == 'MI_example':
@@ -165,7 +165,7 @@ def setDiskImages(self, img_path_1, img_path_2):
     def _createKernelMemoryController(self, cls):
         return MemCtrl(dram = cls(range = self.mem_ranges[0], kvm_map = False))
 
-    def _createMemoryControllers(self, assoc, dcache_size, policy, is_link, link_lat, bypass, flushBufferSize):
+    def _createMemoryControllers(self, assoc, dcache_size, policy, is_link, link_lat, bypass):
         self.kernel_mem_ctrl = self._createKernelMemoryController(DDR3_1600_8x8)
 
         self.mem_ctrl = PolicyManager(range=self.mem_ranges[2], kvm_map=False)
@@ -217,7 +217,6 @@ def _createMemoryControllers(self, assoc, dcache_size, policy, is_link, link_lat
 
         self.loc_mem_ctrl.dram.read_buffer_size = 64
         self.loc_mem_ctrl.dram.write_buffer_size = 64
-        self.loc_mem_ctrl.dram.flush_buffer_size = flushBufferSize
 
         self.far_mem_ctrl.dram.read_buffer_size = 64
         self.far_mem_ctrl.dram.write_buffer_size = 64

diff --git a/plots_1GBdramCache/data-plots.ipynb b/plots_1GBdramCache/data-plots.ipynb